Evaluation of Constant Potential Method in Simulating Electric Double-Layer Capacitors

A major challenge in the molecular simulation of electric double layer capacitors (EDLCs) is the choice of an appropriate model for the electrode. Typically, in such simulations the electrode surface is modeled using a uniform fixed charge on each of the electrode atoms, which ignores the electrode response to local charge fluctuations induced by charge fluctuations in the electrolyte. In this work, we evaluate and compare this Fixed Charge Method (FCM) with the more realistic Constant Potential Method (CPM), [Reed, et al., J. Chem. Phys., 126, 084704 (2007)], in which the electrode charges fluctuate in order to maintain constant electric potential in each electrode. For this comparison, we utilize a simplified LiClO$_4$-acetonitrile/graphite EDLC. At low potential difference ($\Delta\Psi\le 2V$), the two methods yield essentially identical results for ion and solvent density profiles; however, significant differences appear at higher $\Delta\Psi$. At $\Delta\Psi\ge 4V$, the CPM ion density profiles show significant enhancement (over FCM) of "partially electrode solvated" Li$^+$ ions very close to the electrode surface. The ability of the CPM electrode to respond to local charge fluctuations in the electrolyte is seen to significantly lower the energy (and barrier) for the approach of Li$^+$ ions to the electrode surface.Comment: Corrected typo

Classical Fault Analysis of MOS VLSI Circuits

Due to the large cost involved in generating effective input vectors to test MOS circuits, finding ways to reduce this test vector generation cost is of considerable interest. In this paper, empirical results show the fault coverage obtained form MOS transistor-level fault simulation using randomly generated test inputs can be approximated by the fault coverage obtained using the test vectors generated from classical stuck-at-zero and stuck-at-one fault simulation on logic-gate-level circuits. Applying this results, an approach is presented to reduce the cost of test vector generation for MOS circuits