Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

By the continuing downscaling of sub-micron transistors in the range of few to one deca-nanometers, we focus on the increasing relative level of the low-frequency noise in these devices. Large amount of published data and models are reviewed and summarized, in order to capture the state-of-the-art, and to observe that the 1/area scaling of low-frequency noise holds even for carbon nanotube devices, but the noise becomes too large in order to have fully deterministic devices with area less than 10nm×10nm. The low-frequency noise models are discussed from the point of view that the noise can be both intrinsic and coupled to the charge transport in the devices, which provided a coherent picture, and more interestingly, showed that the models converge each to other, despite the many issues that one can find for the physical origin of each model. Several derivations are made to explain crossovers in noise spectra, variable random telegraph amplitudes, duality between energy and distance of charge traps, behaviors and trends for figures of merit by device downscaling, practical constraints for micropower amplifiers and dependence of phase noise on the harmonics in the oscillation signal, uncertainty and techniques of averaging by noise characterization. We have also shown how the unavoidable statistical variations by fabrication is embedded in the devices as a spatial “frozen noise”, which also follows 1/area scaling law and limits the production yield, from one side, and from other side, the “frozen noise” contributes generically to temporal 1/f noise by randomly probing the embedded variations during device operation, owing to the purely statistical accumulation of variance that follows from cause-consequence principle, and irrespectively of the actual physical process. The accumulation of variance is known as statistics of “innovation variance”, which explains the nearly log-normal distributions in the values for low-frequency noise parameters gathered from different devices, bias and other conditions, thus, the origin of geometric averaging in low-frequency noise characterizations. At present, the many models generally coincide each with other, and what makes the difference, are the values, which, however, scatter prominently in nanodevices. Perhaps, one should make some changes in the approach to the low-frequency noise in electronic devices, to emphasize the “statistics behind the numbers”, because the general physical assumptions in each model always fail at some point by the device downscaling, but irrespectively of that, the statistics works, since the low-frequency noise scales consistently with the 1/area law

Variable-range hopping charge transport in organic thin-film transistors

Please cite this article as: O. Marinov, M. J. Deen, J. A. Jiménez-Tejada, C. H. Chen, Variable-range hopping charge transport in organic thin-film transistors, Physics Reports, (2020), 844, 1-105The charge transport in organic thin-film transistors (OTFTs) is assessed in terms of variable range hopping (VRH), by numerical simulations, analytical analyses and comparisons to published experimental results. A numerical simulator, built on the fundamental relations for VRH, provides a simple key dependence that the sum of hopping energy and energy bending under bias is equal to the hopping energy in the bulk material, the latter a bias-independent function of the absolute temperature. This relation binds electrostatics and VRH in OTFTs, at various assumptions for density of states (exponential, double-exponential and normal distributions). It generates and confirms many analytical expressions accumulated over the years for mobility, conductance, potential profiles in the depth of the organic semiconducting film and their relation to bias, film-thickness, also explaining the performance of OTFTs at elevated temperatures. The relations between charges, mobility and bias in OTFTs adhere from the above key dependence. We provide a method to obtain the distribution of the hopping time, which establishes explanations to non-stationary effects in OTFTs, such as dispersive transport, non-reciprocal transitions between on and off-states of the OTFT (usually attributed to gate bias stress and charge build-up), and low-frequency noise in the OTFT channel current.The authors gratefully acknowledge support from the Canada Research Chair (CRC) program and the Natural Sciences and Engineering Research Council (NSERC) of Canada

Variable current transport in polymer thin film transistors

The performance of polymer thin film transistors, made of different semiconducting polymers, depends mostly on the type of polymer and its deposition conditions. For these polymer field-effect transistors (PFETs), the current transport is limited by the carrier injection from the source electrode into the polymer. The disordered polymer molecules near the injection interface randomize and decrease the injection barrier, resulting in a large variation of the PFET characteristics, such as threshold voltage, leakage current, and mobility. The PFET current–voltage characteristics degrade at temperatures higher than 40 °C and the low frequency noise increases by 0.3 dB/°C. © 2004 American Vacuum Society

Photodetection with gate-controlled lateral BJTs from standard CMOS technology

The silicon-based gate-controlled lateral bipolar junction transistor (BJT) is a controllable four-terminal photodetector with very high responsivity at low-light intensities. It is a hybrid device composed of a MOSFET, a lateral BJT, and a vertical BJT. Using sufficient gate bias to operate the MOS transistor in inversion mode, the photodetector allows for increasing the photocurrent gain by 106 at low light intensities when the base-emitter voltage is smaller than 0.4 V, and BJT is off. Two operation modes, with constant voltage bias between gate and emitter/source terminals and between gate and base/body terminals, allow for tuning the photoresponse from sublinear to slightly above linear, satisfying the application requirements for wide dynamic range, high-contrast, or linear imaging. MOSFETs from a standard 0.18-μm triple-well complementary-metal oxide semiconductor technology with a width to length ratio of 8 μm /2 μm and a total area of ∼ 500μm2 are used. When using this area, the responsivities are 16-20 kA/W. © 2001-2012 IEEE

A multisampling time-domain CMOS imager with synchronous readout circuit

A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The proposed multisampling architecture requires only a single bit per pixel memory instead of 8 bits which is typical for time-domain active pixel architectures. The goal is to obtain a time-domain imager with high dynamic range that requires lower number of transistors per pixel in order to achieve higher fill-factor. The maximum frame rate is analyzed as a function of number of bits and array size. The analysis shows that it is possible to achieve high frame rates and operate in video mode having 10 bit pixel data resolution. Also, we present analysis of the impact of comparator offset voltage on the fixed pattern noise. The architecture was implemented in an imager prototype with 32 x 32 pixel array fabricated in AMS CMOS 0.35 mu m and was characterized for sensitivity, noise and color response. The pixel size is 30 mu m x 26 mu m and it is composed of an n+/psub photodiode, a comparator and a D flip-flop with a 16% fill-factor.Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP

A multisampling time-domain CMOS imager with synchronous readout circuit

A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The architecture was implemented in a prototype of imager with 32x32 pixel array fabricated in AMS CMOS 0.35νm and was characterized for sensitivity and color response. The pixel is composed of an n+/psub photodiode, a comparator and a D flip-flop having 16% fill-factor and 30νmx26νm dimensions. The multisampling architecture requires only a 1 bit per pixel memory instead of 8 bits which is typical for time-domain active pixel architectures. The advantage is that the number of transistors in the pixel is low, saving area and providing higher fill-factor. The maximum frame rate is analyzed as a function of number of bits and array size. The analysis shows that it is possible to achieve high frame rates and operation in video mode with 10 bits. Also, we present analysis for the impact of comparator offset voltage in the fixed pattern noise. Copyright 2007 ACM