232 research outputs found
Fault testing quantum switching circuits
Test pattern generation is an electronic design automation tool that attempts
to find an input (or test) sequence that, when applied to a digital circuit,
enables one to distinguish between the correct circuit behavior and the faulty
behavior caused by particular faults. The effectiveness of this classical
method is measured by the fault coverage achieved for the fault model and the
number of generated vectors, which should be directly proportional to test
application time. This work address the quantum process validation problem by
considering the quantum mechanical adaptation of test pattern generation
methods used to test classical circuits. We found that quantum mechanics allows
one to execute multiple test vectors concurrently, making each gate realized in
the process act on a complete set of characteristic states in space/time
complexity that breaks classical testability lower bounds.Comment: (almost) Forgotten rewrite from 200
Testing a Quantum Computer
The problem of quantum test is formally addressed. The presented method
attempts the quantum role of classical test generation and test set reduction
methods known from standard binary and analog circuits. QuFault, the authors
software package generates test plans for arbitrary quantum circuits using the
very efficient simulator QuIDDPro[1]. The quantum fault table is introduced and
mathematically formalized, and the test generation method explained.Comment: 15 pages, 17 equations, 27 tables, 8 figure
Memristor-Based Volistor Gates Compute Logic with Low Power Consumption
We introduce a novel volistor logic gate which uses voltage as input and resistance as output. Volistors rely on the diode-like behavior of rectifying memristors. We show how to realize the first logic level, counted from the input, of any Boolean function with volistor gates in a memristive crossbar network. Unlike stateful logic, there is no need to store the inputs as resistances, and computation is performed directly. The fan-in and fan-out of volistor gates are large and different from traditional memristor circuits. Compared to solely memristive stateful logic, a combination of volistors and stateful inhibition gates can significantly reduce the number of operations required to calculate arbitrary multi-output Boolean functions. The power consumption of volistor logic is computed and compared with the power consumption of stateful logic using the simulation results obtained by LTspice—when implemented in a 1 × 8 or an 8 × 1 crosspoint array, volistors consume significantly less power
Quantum Algorithms for Unate and Binate Covering Problems with Application to Finite State Machine Minimization
Covering problems find applications in many areas of computer science and engineering, such that numerous combinatorial problems can be formulated as covering problems. Combinatorial optimization problems are generally NPhard problems that require an extensive search to find the optimal solution. Exploiting the benefits of quantum computing, we present a quantum oracle design for covering problems, taking advantage of Grover’s search algorithm to achieve quadratic speedup. This paper also discusses applications of the quantum counter in unate covering problems and binate covering problems with some important practical applications, such as finding prime implicants of a Boolean function, implication graphs, and minimization of incompletely specified Finite State Machines
Minimization of Quantum Circuits using Quantum Operator Forms
In this paper we present a method for minimizing reversible quantum circuits
using the Quantum Operator Form (QOF); a new representation of quantum circuit
and of quantum-realized reversible circuits based on the CNOT, CV and
CV quantum gates. The proposed form is a quantum extension to the
well known Reed-Muller but unlike the Reed-Muller form, the QOF allows the
usage of different quantum gates. Therefore QOF permits minimization of quantum
circuits by using properties of different gates than only the multi-control
Toffoli gates. We introduce a set of minimization rules and a pseudo-algorithm
that can be used to design circuits with the CNOT, CV and CV quantum
gates. We show how the QOF can be used to minimize reversible quantum circuits
and how the rules allow to obtain exact realizations using the above mentioned
quantum gates.Comment: 11 pages, 14 figures, Proceedings of the ULSI Workshop 2012 (@ISMVL
2012
Cellular Automata Realization of Regular Logic
This paper presents a cellular-automatic model of a reversible regular structure called Davio lattice. Regular circuits are investigated because of the requirement of future (nano-) technologies where long wires should be avoided. Reversibility is a valuable feature because it means much lower energy dissipation. A circuit is reversible if the number of its inputs equals the number of its outputs and there is a one-to-one mapping between spaces of input vectors and output vectors. It is believed that one day regular reversible structures will be implemented as nanoscale 3-dimensional chips. This paper introduces the notion of the Toffoli gate and its cellular-automatic implementation, as well as an example of the Davio lattice built exclusively of Toffoli gates and run on a special cellular automaton called CAM-Brain Machine (CBM)
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