NASA Standard GAS Can Satellite

This paper describes a new direction in small low cost spacecraft. This 150 pound satellite provides access to conduct experiments in space on an economical and short term basis. It can be used by commercial as well as scientific institutions. Currently called the XSAT, it was developed by NASA in cooperation with Defense Systems Inc. (DSI) of McLean, Virginia. XSAT provides for experimental payloads up to 50 pounds, 50 watt hours per day, one megabyte data storage, three day command memory and packetized protocol. Structural and thermal designs can handle worst case loads of the STS manned launch vehicle. XSAT can be operated by an experimenter using a personal computer from a ground-based station either locally or over normal telephone lines. An Attitude Control System (ACS) and/or propulsion system is added to XSAT on a mission peculiar basis in order to accommodate the requirements of each specific payload

Incremental QBF Solving

We consider the problem of incrementally solving a sequence of quantified Boolean formulae (QBF). Incremental solving aims at using information learned from one formula in the process of solving the next formulae in the sequence. Based on a general overview of the problem and related challenges, we present an approach to incremental QBF solving which is application-independent and hence applicable to QBF encodings of arbitrary problems. We implemented this approach in our incremental search-based QBF solver DepQBF and report on implementation details. Experimental results illustrate the potential benefits of incremental solving in QBF-based workflows.Comment: revision (camera-ready, to appear in the proceedings of CP 2014, LNCS, Springer

Building Strategies into QBF Proofs

Strategy extraction is of great importance for quantified Boolean formulas (QBF), both in solving and proof complexity. So far in the QBF literature, strategy extraction has been algorithmically performed from proofs. Here we devise the first QBF system where (partial) strategies are built into the proof and are piecewise constructed by simple operations along with the derivation. This has several advantages: (1) lines of our calculus have a clear semantic meaning as they are accompanied by semantic objects; (2) partial strategies are represented succinctly (in contrast to some previous approaches); (3) our calculus has strategy extraction by design; and (4) the partial strategies allow new sound inference steps which are disallowed in previous central QBF calculi such as Q-Resolution and long-distance Q-Resolution. The last item (4) allows us to show an exponential separation between our new system and the previously studied reductionless long-distance resolution calculus. Our approach also naturally lifts to dependency QBFs (DQBF), where it yields the first sound and complete CDCL-style calculus for DQBF, thus opening future avenues into CDCL-based DQBF solving

Formal Methods in Computer-aided Design

The VLSI CAD flow encompasses an abundance of critical NP-complete and PSPACE-complete problems. Instead of developing a dedicated algorithm for each, the trend during the last decade has been to encode them in formal languages, such as Boolean satisfiability (SAT) and quantified Boolean formulas (QBFs), and focus academic resources on improving SAT and QBF solvers. The significant progress of these solvers has validated this strategy. This dissertation contributes to the further advancement of formal techniques in CAD. Today, the verification and debugging of increasingly complex RTL designs can consume up to 70% of the VLSI design cycle. In particular, RTL debug is a manual, resource-intensive task in the industry. The first contribution of this thesis is an in-depth examination of the factors affecting the theoretical computational complexity of debugging. It is established that most variations of the debugging problem are NP-complete. Automated debugging tools return all potential error sources in the RTL, called solutions, that can explain a given failing error trace. Finding each solution requires a separate call to a formal engine, which is computationally expensive. The second contribution of this dissertation comprises techniques for reducing the number of such iterations, by leveraging dominance relationships between RTL blocks to imply solutions. Extensive experiments on industrial designs show a three-fold reduction in the number of formal engine calls due to solution implications, resulting in a 1.64x overall speed-up. The third contribution aims to advance the state-of-the-art of QBF solvers, whose progress has not been as impressive as that of SAT solvers. We present a framework for using complete dominators to preprocess and reduce QBFs with an inherent circuit structure, which is common in encodings of PSPACE-complete CAD problems. Experiments show that three modern QBF solvers together solve 55% of preprocessed QBF instances, compared to none without preprocessing. The final contribution consists of a series of QBF encodings for evaluating the reconfigurability of partially programmable circuits (PPCs). The metrics of fault tolerance, design error tolerance and engineering change coverage are defined for PPCs and encoded using QBFs. These formulations along with experimental results demonstrate the theoretical and practical appropriateness of QBFs for dealing with reconfigurability.Ph

On Statistical Timing Analysis with Inter- and Intra-die Variations

In this paper, we highlight a fast, effective and practical statistical approach that deals with inter and intra-die variations in VLSI chips. Our methodology is applied to a number of random variables while accounting for spatial correlations. Our methodology sorts the Probability Density Functions (PDFs) of the critical paths of a circuit based on a confidence-point. We show the mathematical accuracy of our method as well as implement a typical program to test it on various benchmarks. We find that worst-case analysis overestimates path delays by more than 50 % and that a path’s probabilistic rank with respect to delay is very different from its deterministic rank.

Bourj Hammoud : logiques municipales entre aménagement, développement et identité patrimoniale

Est évoqué ici l’ensemble des espaces et équipements publics constitués au cours du xxe siècle dans la municipalité de Bourj Hammoud, au nord-est de Beyrouth, peuplée essentiellement d’Arméniens exilés après 1917. On aborde aussi les effets négatifs résultant de la pression exercée par des logiques d’aménagement plus adaptées à la capitale qu’à ses périphéries, ainsi que les actions envisagées par la municipalité pour sauvegarder le patrimoine collectif.This paper evokes the public spaces and facilities which have been created during the 20th century at Bourj Hammoud’s Municipality, (North-East of Beirut); this neighbourhood is mainly populated with Armenians who were exiled after the year 1917. We also talk about negative effects resulting from pressures imposed by planning logics that are more suitable for a capital than its peripheries, as well as municipal initiatives aiming at preserving the collective heritage.تذكر هذه الورقة مجمل الفضاءات العامة التي تشكلت خلال القرن العشرين في بلدية برج حمود، شمال شرق بيروت، المأهولة بشكلٍ أساسي بالأرمن الذين تم نفيهم بعد العام 1917. كما تسلط الورقة الضوء على المفاعيل السلبية الناتجة عن الضغط الذي تمارسه ضروب منطق التخطيط المتكيف مع العاصمة أكثر من أطرافها، بالإضافة إلى النشاطات التي تخطّط البلدية للقيام بها من أجل الحفاظ على التراث الجماعي

A Performance-Driven QBF-Based Iterative Logic Array Representation with Applications to Verification, Debug and Test

Abstract — Many CAD for VLSI techniques use time-frame expansion, also known as the Iterative Logic Array representation, to model the sequential behavior of a system. Replicating industrialsize designs for many time-frames may impose impractically excessive memory requirements. This work proposes a performancedriven, succinct and parametrizable Quantified Boolean Formula (QBF) satisfiability encoding and its hardware implementation for modeling sequential circuit behavior. This encoding is then applied to three notable CAD problems, namely Bounded Model Checking (BMC), sequential test generation and design debugging. Extensive experiments on industrial circuits confirm outstanding run-time and memory gains compared to state-of-the-art techniques, promoting the use of QBF in CAD for VLSI. I