Achieving the physical limits of the bounded-storage model

Secure two-party cryptography is possible if the adversary's quantum storage device suffers imperfections. For example, security can be achieved if the adversary can store strictly less then half of the qubits transmitted during the protocol. This special case is known as the bounded-storage model, and it has long been an open question whether security can still be achieved if the adversary's storage were any larger. Here, we answer this question positively and demonstrate a two-party protocol which is secure as long as the adversary cannot store even a small fraction of the transmitted pulses. We also show that security can be extended to a larger class of noisy quantum memories.Comment: 10 pages (revtex), 2 figures, v2: published version, minor change

Design of Ad Hoc Wireless Mesh Networks Formed by Unmanned Aerial Vehicles with Advanced Mechanical Automation

Ad hoc wireless mesh networks formed by unmanned aerial vehicles (UAVs) equipped with wireless transceivers (access points (APs)) are increasingly being touted as being able to provide a flexible "on-the-fly" communications infrastructure that can collect and transmit sensor data from sensors in remote, wilderness, or disaster-hit areas. Recent advances in the mechanical automation of UAVs have resulted in separable APs and replaceable batteries that can be carried by UAVs and placed at arbitrary locations in the field. These advanced mechanized UAV mesh networks pose interesting questions in terms of the design of the network architecture and the optimal UAV scheduling algorithms. This paper studies a range of network architectures that depend on the mechanized automation (AP separation and battery replacement) capabilities of UAVs and proposes heuristic UAV scheduling algorithms for each network architecture, which are benchmarked against optimal designs.Comment: 12 page

Verification of the FtCayuga fault-tolerant microprocessor system. Volume 2: Formal specification and correctness theorems

Presented here is a formal specification and verification of a property of a quadruplicately redundant fault tolerant microprocessor system design. A complete listing of the formal specification of the system and the correctness theorems that are proved are given. The system performs the task of obtaining interactive consistency among the processors using a special instruction on the processors. The design is based on an algorithm proposed by Pease, Shostak, and Lamport. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, providing certain preconditions hold, using a computer aided design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover

Moving formal methods into practice. Verifying the FTPP Scoreboard: Results, phase 1

This report documents the Phase 1 results of an effort aimed at formally verifying a key hardware component, called Scoreboard, of a Fault-Tolerant Parallel Processor (FTPP) being built at Charles Stark Draper Laboratory (CSDL). The Scoreboard is part of the FTPP virtual bus that guarantees reliable communication between processors in the presence of Byzantine faults in the system. The Scoreboard implements a piece of control logic that approves and validates a message before it can be transmitted. The goal of Phase 1 was to lay the foundation of the Scoreboard verification. A formal specification of the functional requirements and a high-level hardware design for the Scoreboard were developed. The hardware design was based on a preliminary Scoreboard design developed at CSDL. A main correctness theorem, from which the functional requirements can be established as corollaries, was proved for the Scoreboard design. The goal of Phase 2 is to verify the final detailed design of Scoreboard. This task is being conducted as part of a NASA-sponsored effort to explore integration of formal methods in the development cycle of current fault-tolerant architectures being built in the aerospace industry

Simple approach to approximate quantum error correction based on the transpose channel

We demonstrate that there exists a universal, near-optimal recovery map—the transpose channel—for approximate quantum error-correcting codes, where optimality is defined using the worst-case fidelity. Using the transpose channel, we provide an alternative interpretation of the standard quantum error correction (QEC) conditions and generalize them to a set of conditions for approximate QEC (AQEC) codes. This forms the basis of a simple algorithm for finding AQEC codes. Our analytical approach is a departure from earlier work relying on exhaustive numerical search for the optimal recovery map, with optimality defined based on entanglement fidelity. For the practically useful case of codes encoding a single qubit of information, our algorithm is particularly easy to implement

Verification of the FtCayuga fault-tolerant microprocessor system. Volume 1: A case study in theorem prover-based verification

The design and formal verification of a hardware system for a task that is an important component of a fault tolerant computer architecture for flight control systems is presented. The hardware system implements an algorithm for obtaining interactive consistancy (byzantine agreement) among four microprocessors as a special instruction on the processors. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, provided certain preconditions hold. An assumption is made that the processors execute synchronously. For verification, the authors used a computer aided design hardware design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover