High-resolution strain sensing on steel by Silicon-On-Insulator flexural resonators fabricated with chip-level vacuum packaging

This paper reports on the fabrication and characterization of high-resolution strain sensors for steel based on Silicon On Insulator flexural resonators manufactured with chip-level LPCVD vacuum packaging. The sensors present high sensitivity (120 Hz/??), very high resolution (4 n?), low drift, and near-perfect reversibility in bending tests performed in both tensile and compressive strain regimes

Strain sensing on steel surfaces using vacuum packaged MEMS resonators

The paper presents a technology for strain sensing on steel using resonant MEMS packaged in vacuum. For this purpose, a custom sensor fabrication technology and a novel vacuum packaging technique have been developed. The MEMS sensors have been fabricated by surface micromachining of thick (15 μm) Silicon On Insulator substrates with heavily doped handle layers View the MathML source(ρ = 0.005 Ωcm). Using this process, Double-Ended Tuning Fork (DETF) parallel-plate resonators with reduced coupling gaps (less than 1 μm) have been fabricated, using a high-performance Deep Reactive Ion Etching performed on submicrometer features realized by near-UV lithography combined with a maskless line narrowing technique. The devices have been bonded to a thin steel bar by epoxy glue, packaged in vacuum and tested by applying strain to the bar, showing good tolerances to packaging parasitics, measurement reversibility, and strain sensitivity of View the MathML source10Hz/με

Fabrication and testing of a high resolution extensometer based on resonant MEMS strain sensors

A novel type of linear extensometer with exceptionally high resolution of 4 nm based on MEMS resonant strain sensors bonded on steel and operating in a vacuum package is presented. The tool is implemented by means of a steel thin bar that can be pre-stressed in tension within two fixing anchors. The extension of the bar is detected by using two vacuum-packaged resonant MEMS double-ended tuning fork (DETF) sensors bonded on the bar with epoxy glue, one of which is utilized for temperature compensation. Both sensors are driven by a closed loop self-oscillating transresistance amplifier feedback scheme implemented on a PCB (Printed Circuit Board). On the same board, a microcontroller-based frequency measurement circuit is also implemented, which is able to count the square wave fronts of the MEMS oscillator output with a resolution of 20 nsec. The system provides a frequency noise of 0.2 Hz corresponding to an extension resolution of 4 nm for the extensometer. Nearly perfect temperature compensation of the frequency output is achieved in the temperature range 20-35°C using the reference sensor

Design and prototyping of a MEMS-based crackmeter for structural monitoring

Crack measurement is an important technique in structural monitoring, which is presently implemented with macroscopic devices characterized by rather demanding power consumption requirements. Such devices, consequently, are not very well suited for wireless operation, which is particularly interesting for specific applications involving deployment of a number of crackmeters within large-scale ageing infrastructures with possibility of remote, on-demand sensor interrogation. This paper reports about the research work related to the design and prototyping of a novel crackmeter suited for wireless structural monitoring realized with silicon MEMS strain sensors with high resolution, very low power operation and small size

Processing-Induced Electrically Active Defects in Black Silicon Nanowire Devices

Silicon nanowires (Si NWs) are widely investigated nowadays for implementation in advanced energy conversion and storage devices, as well as many other possible applications. Black silicon (BSi)-NWs are dry etched NWs that merge the advantages related to low-dimensionality with the special industrial appeal connected to deep reactive ion etching (RIE). In fact, RIE is a well established technique in microelectronics manufacturing. However, RIE processing could affect the electrical properties of BSi-NWs by introducing deep states into their forbidden gap. This work applies deep level transient spectroscopy (DLTS) to identify electrically active deep levels and the associated defects in dry etched Si NW arrays. Besides, the successful fitting of DLTS spectra of BSi-NWs-based Schottky barrier diodes is an experimental confirmation that the same theoretical framework of dynamic electronic behavior of deep levels applies in bulk as well as in low dimensional structures like NWs, when quantum confinement conditions do not occur. This has been validated for deep levels associated with simple pointlike defects as well as for deep levels associated with defects with richer structures, whose dynamic electronic behavior implies a more complex picture

3C-SiC Growth on Inverted Silicon Pyramids Patterned Substrate

This work reports on the properties of cubic silicon carbide (3C-SiC) grown epitaxially on a patterned silicon substrate composed of squared inverted silicon pyramids (ISP). This compliant substrate prevents stacking faults, usually found at the SiC/Si interface, from reaching the surface. We investigated the effect of the size of the inverted pyramid on the epilayer quality. We noted that anti-phase boundaries (APBs) develop between adjacent faces of the pyramid and that the SiC/Si interfaces have the same polarity on both pyramid faces. The structure of the heterointerface was investigated. Moreover, due to the emergence of APB at the vertex of the pyramid, voids buried on the epilayer form. We demonstrated that careful control of the growth parameters allows modification of the height of the void and the density of APBs, improving SiC epitaxy quality

Integration of InGaP/GaAs/Ge triple-junction solar cells on deeply patterned silicon substrates

We report preliminary results on InGaP/InGaAs/Ge photovoltaic cells for concentrated terrestrial applications, monolithically integrated on engineered Si(001) substrates. Cells deposited on planar Ge/Si(001) epilayers, grown by plasma-enhanced chemical vapor deposition, provide good efficiency and spectral response, despite the small thickness of the Ge epilayers and a threading dislocation density as large as 107/cm2. The presence of microcracks generated by the thermal misfit is compensated by a dense collection grid that avoids insulated areas. In order to avoid the excessive shadowing introduced by the use of a dense grid, the crack density needs to be lowered. Here, we show that deep patterning of the Si substrate in blocks can be an option, provided that a continuous Ge layer is formed at the top, and it is suitably planarized before the metalorganic chemical vapor deposition. The crack density is effectively decreased, despite that the efficiency is also lowered with respect to unpatterned devices. The reasons of this efficiency reduction are discussed, and a strategy for improvement is proposed and explored. Full morphological analysis of the coalesced Ge blocks is reported, and the final devices are tested under concentrated AM1.5D spectrum. Copyright © 2016 John Wiley & Sons, Ltd