Low-loss, compact, spot-size-converter based vertical couplers for photonic integrated circuits

Funding: (i) European Union Horizon H2020 Programme (H2020-ICT27-2015, COSMICC No. 688516). (ii) European Union Research Council (ERC) starting grant 337508.In recent years, the monolithic integration of new materials such as SiN, Ge and LiNbO3 on silicon (Si) has become important to the Si photonics community due to the possibility of combining the advantages of both material systems. However, efficient coupling between the two different layers is challenging. In this work, we present a spot size converter based on a two-tier taper structure to couple the optical mode adiabatically between Si and SiN. The fabricated devices show a coupling loss as low as 0.058 dB  ±  0.01 dB per transition at 1525 nm. The low coupling loss between the Si to SiN, and vice versa, reveals that this interlayer transition occurs adiabatically for short taper lengths (<200 µm). The high refractive index contrast between the Si and SiN is overcome by matching the optical impedance. The proposed two-tier taper structure provides a new platform for optoelectronic integration and a route towards 3D photonic integrated circuits.PostprintPeer reviewe

A versatile silicon-silicon nitride photonics platform for enhanced functionalities and applications

Silicon photonics is one of the most prominent technology platforms for integrated photonics and can support a wide variety of applications. As we move towards a mature industrial core technology, we present the integration of silicon nitride (SiN) material to extend the capabilities of our silicon photonics platform. Depending on the application being targeted, we have developed several integration strategies for the incorporation of SiN. We present these processes, as well as key components for dedicated applications. In particular, we present the use of SiN for athermal multiplexing in optical transceivers for datacom applications, the nonlinear generation of frequency combs in SiN micro-resonators for ultra-high data rate transmission, spectroscopy or metrology applications and the use of SiN to realize optical phased arrays in the 800&ndash;1000 nm wavelength range for Light Detection And Ranging (LIDAR) applications. These functionalities are demonstrated using a 200 mm complementary metal-oxide-semiconductor (CMOS)-compatible pilot line, showing the versatility and scalability of the Si-SiN platform

Integrated lasers on silicon for optical communications

We review our work on integrated lasers for optical communications. An InP-based multilayer stack containing Al-based quantum wells with optical gain in the telecom window is bonded onto a silicon-on-insulator wafer with patterned photonic circuits and cavities. Ring-based widely tunable lasers and narrow linewidth DFB lasers are demonstrated

Process Integration of Photonic interposer for Chiplet-based 3D Systems

International audienceThis paper presents the integration of a photonic interposer designed to host 4 chiplets (28nm FDSOI) each integrating 16 cores and 6 RX/TX routers (28nm FDSOI) 3D stacked for many-core systems.Exascale computer has been one of the main driver in the field of HPC and Datacom and has recently been reached mainly thanks to co-design approach. The next breakthrough in HPC integration will probably come through photonic technology and optical network-on-chip (ONoC) to overpass the bandwidth and the latency limitations of electrical links [1]. This paper will detail the integration and the fabrication on the 200mm Leti platform of a Si photonic interposer on SOI wafers featuring Si 310nm on 800nm thick buried oxide (BOX). The photonic circuit operating at 1310nm wavelength is composed of silicon passive structures (Rib waveguides, SPGC, …) and actives devices (SiGeSi photodiodes, PIN ring modulators). TiN heaters embedded in SiO2 above the ring modulators allow tuning wavelength resonance of the device. Active devices and heaters are connected to the BEOL using W contacts. The TSV middle process (12x100µm) is detailed with the implementation of SiN sacrificial layer above photonic FEOL to protect W plugs. The 4 metals layers back-end process with 2 layers optimized for RF signals is also introduced as well as micropillars (Fig 1 - right). The backside processing is then explained with the interposer thinning at 100µm and a thermal cavity etching above the heatersThe propagation losses are measured on RIB and DRIB structures and the insertion losses on SPGC structures both at the end of the FEOL and the BEOL process. The impact of the thermal back-end processes is then discussed.The TSV mid resistance have been evaluated with Kelvin test structure and daisy chains. The resistance is evaluated 95 % with the nominal diameter of 12µm. The dispersion of resistance values with the TSV diameter is also studied in the range of ± 1µm. The BEOL metal layers are characterized with DC test structures after each metal layer to evaluate the metal sheet resistance, the via resistance, the yield and the leakage current. The evolution of the metal and via performances within the processes is studied. Lock-in thermography analysis is performed on daisy chains and completed with Focused ion beam (FIB) cross-sections.The study has qualified all individual integration blocks required for the functional ONoC system developed currently in our group

Low-Threshold, High-Power On-Chip Tunable III-V/Si Lasers with Integrated Semiconductor Optical Amplifiers

Heterogeneously integrated III-V/Si lasers and semiconductor optical amplifiers (SOAs) are key devices for integrated photonics applications requiring miniaturized on-chip light sources, such as in optical communications, sensing, or spectroscopy. In this work, we present a widely tunable laser co-integrated with a semiconductor optical amplifier in a heterogeneous platform that combines AlGaInAs multiple quantum wells (MQWs) and InP-based materials with silicon-on-insulator (SOI) wafers containing photonic integrated circuits. The co-integrated device is compact, has a total device footprint of 0.5 mm2, a lasing current threshold of 10 mA, a selectable wavelength tuning range of 50 nm centered at &lambda; = 1549 nm, a fiber-coupled output power of 10 mW, and a laser linewidth of &nu; = 259 KHz. The SOA provides an on-chip gain of 18 dB/mm. The total power consumption of the co-integrated devices remains below 0.5 W even for the most power demanding lasing wavelengths. Apart from the above-mentioned applications, the co-integration of compact widely tunable III-V/Si lasers with on-chip SOAs provides a step forward towards the development of highly efficient, portable, and low power systems for wavelength division multiplexed passive optical networks (WDM-PONs)

Hybrid III-V on Silicon Integrated Distributed Feedback Laser and Ring Resonator for 25 Gb/s Future Access Networks

International audienceWe report on a fully integrated hybrid III-V on a silicon distributed feedback laser integrated with a ring resonator. We demonstrate an enhanced extinction ratio up to 5 dB at 25 Gb/s of the distributed feedback laser when the ring-resonator is finely tuned. We validated the transmitter with a 20-km transmission with only 2.5-dB penalty and 20-dB power budget

3D Silicon Photonic Interposer Process Integration for Chiplet based 3D Systems

International audienceThis paper presents the process integration and technology development of a photonic interposer designed to host 4 chiplets (28 nm FDSOI) each integrating 16 cores and 6 RX/TX drivers (28 nm FDSOI) 3D stacked for many-core systems