G-Centre formation and behaviour in a silicon on insulator platform by carbon ion implantation and Proton irradiation

The interest in the G-centre is driven by reports that it can lase in silicon. To further this, the transfer of this technology from bulk silicon to a silicon-on-insulator (SOI) platform is an essential requirement to progress to lasing and optical amplification on silicon. We report on the efficient generation of the lasing G-centre in SOI substrates by proton irradiation of carbon ion implants. Following carbon implantation samples were annealed and then proton irradiated to form the G-centre and characterized by photoluminescence measurements. The temperature dependence of the emission and the behaviour of the G-centre with post proton annealing were investigated and results are compared with identical implants in control samples of bulk silicon. Overall, we find that the optically active G-centre can be up to 300% brighter and has better survivability over a wider process window in SOI than in bulk silicon

Impact of Salicide and Source/Drain Implants on Leakage Current and Sheet Resistance in 45nm NMOS Device

In this paper, we investigate the impact of Source/Drain (S/D) implant and salicide on poly sheet resistance (RS) and leakage current (I Leak ) in 45nm NMOS device performance. The experimental studies were conducted under varying four process parameters, namely Halo implant, Source/Drain Implant, Oxide Growth Temperature and Silicide Anneal Temperature. Taguchi Method was used to determine the settings of process parameters. The level of importance of the process parameters on the RS and I Leak were determined by using analysis of variance (ANOVA). The fabrication of the devices was performed by using fabrication simulator of ATHENA. The electrical characterization of the device was implemented by using electrical characterization simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing the process parameters. The optimum process parameter combination was obtained by using the analysis of signal-tonoise (S/N) ratio. In this research, the most effective process parameters with respect to poly sheet resistance and leakage current are silicide anneal temperature (88%) and S/D implant (62%) respectively. Whereas the second ranking factor affecting the poly sheet resistance and leakage current are S/D implant (12%) and silicide anneal temperature (20%) respectively. As conclusions, S/D implant and silicide annealtemperature have the strongest effect on the response characteristics. The results show that the R S and I Leak after optimizations approaches are 42.28□□ and 0.1186mA/□m respectivel

Effect of Low Temperature on The Fabrication of Microring Resonator by Wet Etching

Research related to semiconductor devices often relies on wafer fabrication. The fabrication of Silicon (Si) based devices by anisotropic wet etching can be affected by many etching parameters such as etching temperature, crystal orientation and percent of composition. Most of the anisotropic wet etchings by KOH solution done before were conducted at temperature over 70°C. We found that the temperatures are not suitable to fabricate ring waveguide as the waveguide wall will collapse at such high temperature. This study reports the etching characteristics of Si in KOH solution with 35% concentration at the temperature below 70°C. The etched wafer is targeted to be the basic structure for Microring Resonators (MRRs) based devices. This technique provides not only lower cost as compared to other etching technique, but also simple preparation. We found that low temperature manage to mold a good ring waveguide with low tendency to form rectangular structure due to crystal orientation. At 40°C, the best waveguide formation was obtained with a smooth waveguide surface, experiencing an etching rate of 0.066 μ min-1 and an appreciable ring waveguide structure. The effect of the low temperature on the fabrication of the MRRs devices has been investigated and studied

Modeling of SOI-based MRR by Coupled Mode Theory using Lateral Coupling Configuration

We present the modeling of a first order waveguide-coupled microring resonator (MRR) by coupled mode theory (CMT) using transfer matrix model. The design topology is based on the lateral coupling configuration and single mode propagation which is integrated on a Silicon-on-Insulator (SOI) platform. Performance parameters including Free Spectral Range (FSR) and Quality Factor (Q-factor) are investigated. For verification, we compare these results with the results obtained from the Finite Difference Time Domain (FDTD) commercially available software. We found that both results agree well with each other

Optimal solution in producing 32-nm CMOS technology transistor with desired leakage current

The objective of this paper is to optimize the process parameters of 32-nm CMOS process to get minimum leakage current. Four process parameters were chosen, namely: (i) source-drain implantation, (ii) source-drain compensation implantation, (iii) halo implantation time, and (iv) silicide annealing time. The Taguchi method technique was used to design the experiment. Two noise factors were used that consist of four measurements for each row of experiment in the L9 array, thus leading to a set of experiments consisting of 36 runs. The simulator of ATHENA and ATLAS were used for MOSFET fabrication process and electrical characterization, respectively. The results clearly show that the compensation implantation (46%) has the most dominant impact on the resulting leakage current in NMOS device, whereas source-drain (S/D) implantation was the second ranking factor (35%). The percent effects on signal-to-noise ratio (SNR) of silicide annealing temperature and halo implantation are much lower being 12% and 7%, respectively. For the PMOS device, halo implantation was defined as an adjustment factor because of its minimal effect on SNR and highest on the means (43%). Halo implantation doping as the optimum solution for fabricating the 32-nm NMOS transistor is 2.38×10¹³atom/cm³. As conclusion, this experiment proves that the Taguchi analysis can be effectively used in finding the optimum solution in producing 32-nm CMOS transistor with acceptable leakage current, well within International Technology Roadmap for Semiconductor (ITRS) prediction

Comparison of mesa and device diameter variation in double wafer-fused multi quantum-well, long-wavelength, vertical cavity surface emitting lasers

Long-wavelength vertical-cavity surface-emitting lasers (LW-VCSELs) have profound advantages compared to traditional edge-emitting lasers offering improved properties with respect to mode selectivity, fibre coupling, threshold currents and integration into 2D arrays or with other electronic devices. Its commercialization is gaining momentum as the local and access network in optical communication system expand. Numerical modeling of LW-VCSEL utilizing wafer-fused InP-based multi-quantum wells (MQW) and GaAs-based distributed Bragg reflectors (DBRs) is presented in this paper. Emphasis is on the device and mesa/pillar diameter design parameter comparison and its effect on the device characteristics

Influence of Optimization of Process Parameters on Threshold Voltage for Development of HfO2/TiSi2 18 nm PMOS

Manufacturing a 18-nm transistor requires a variety of parameters, materials, temperatures, and methods. In this research, HfO2 was used as the gate dielectric ad TiO2 was used as the gate material. The transistor HfO2/TiSi2 18-nm PMOS was invented using SILVACO TCAD. Ion implantation was adopted in the fabrication process for the method’s practicality and ability to be used to suppress short channel effects. The study involved ion implantation methods: compensation implantation, halo implantation energy, halo tilt, and source–drain implantation. Taguchi method is the best optimization process for a threshold voltage of HfO2/TiSi2 18-nm PMOS. In this case, the method adopted was Taguchi orthogonal array L9. The process parameters (ion implantations) and noise factors were evaluated by examining the Taguchi’s signal-to-noise ratio (SNR) and nominal-the-best for the threshold voltage (VTH). After optimization, the result showed that the VTH value of the 18-nm PMOS device was -0.291339

Influence of calcination temperatures on structure and magnetic properties of calcium ferrite nanoparticles synthesized via sol-gel method

Calcium ferrite (CaFe2O4) nanoparticles using calcium nitrate and ferric nitrate as starting materials, and supplemented with citric acid as chelating agent was carried out. This mixture was synthesized through a sol-gel method and then calcined at 550 °C, 650 °C, and 750 °C. The effects of calcination temperatures on the crystalline structure, the surface morphology and the magnetic properties of CaFe2O4 NPs were observed. The orthorhombic structure of calcium ferrite NPS was analysed through an X-ray diffraction. The size of calcined samples at 550 °C, 650 °C, 750 °C were (13.59 nm), (18.9 nm), and (46.12 nm), respectively. Magnetic analysis was measured by using a vibrating sample magnetometer (VSM). The magnetic saturation (Ms) of samples calcined at 550 °C was found to possess the highest value of magnetic property; 80.33 emu/g

Statistical design of ultra-thin SiO2 for nanodevices

A study was performed on a series of ultra thin SiO2 films in order to determine the factors affecting the oxide growth and also the effect of temperature to the film surface roughness. The samples of ultra thin SiO2 were prepared through a dry oxidation method using a high temperature furnace. There are three levels of temperature used, that is 900, 950 and 1000°C and the samples were grown at 0.333 litre/min, 0.667 liter/min and 1 liter/min oxygen flow rate and different oxidation times of 1, 2 and 3 minutes. The thickness was determined using an ellipsometer and the micro morphology of the oxide surface was obtained by using an atomic force microscope (AFM). The thickness of the oxide ranged from 1 to 5 nm. All the data has been interpreted using Taguchi’s method to analyze the most affecting factors in producing an ultra thin silicon dioxide. The optimum parameters are 900°C, 0.333 litre/min and at 1 minute time. The most influential parameter is temperature. The temperature also affects the surface roughness. The AFM result of 950°C with RMS value of 0.1088 nm is better than the 900°C oxide with RMS value 0.4553 nm. This shows that oxides need to be grown at a higher temperature to provide better surface roughness which is also important in ultra thin gate oxide characteristics

Influence of Optimization of Process Parameters on Threshold Voltage for Development of HfO

Manufacturing a 18-nm transistor requires a variety of parameters, materials, temperatures, and methods. In this research, HfO2 was used as the gate dielectric ad TiO2 was used as the gate material. The transistor HfO2/TiSi2 18-nm PMOS was invented using SILVACO TCAD. Ion implantation was adopted in the fabrication process for the method’s practicality and ability to be used to suppress short channel effects. The study involved ion implantation methods: compensation implantation, halo implantation energy, halo tilt, and source–drain implantation. Taguchi method is the best optimization process for a threshold voltage of HfO2/TiSi2 18-nm PMOS. In this case, the method adopted was Taguchi orthogonal array L9. The process parameters (ion implantations) and noise factors were evaluated by examining the Taguchi’s signal-to-noise ratio (SNR) and nominal-the-best for the threshold voltage (VTH). After optimization, the result showed that the VTH value of the 18-nm PMOS device was -0.291339