Ultra-thin biocompatible implantable chip for bidirectional communication with peripheral nerves

To realize optimal recording and stimulation of peripheral nerve cells, a CMOS chip is made with a multitude of electrodes which can be individually addressed in order to select after implantation the 16 best positioned electrodes. Since the Foreign Body Reaction should be minimal for optimum electrode-nerve contact, the CMOS chip is thinned down to 35um and fully packaged resulting in a 75um thin encapsulated chip. The chip is embedded in a biocompatible stack consisting of polymers and inorganic diffusion barriers deposited using atomic layer deposition (ALD). A biocompatible metallization is realized using gold and platinum sandwiched between polymers and ALD layers for flexible interconnects, and iridium oxide (IrOx) is selected as electrode material for optimal charge injection during stimulation. After this dedicated packaging based on the FITEP technology platform (Flexible Implantable Thin Electronic Package), the CMOS chip is still fully functional, which was tested dry (in air) as well as during submersion in saline. The form factor of the packaged chip is optimized for intra-fascicular implantation with minimum tissue damage. First acute in vivo stimulation tests proved that the stimulation capabilities of the IrOx electrodes are very good

Architectural compensation techniques for analog inaccuracies in ΔΣanalog-to-digital converters

Delta-sigma analog-to-digital converters (ADCs) are suitable for many applications due to several advantages such as relaxed anti-aliasing filter, high signal-to noise and distortion ratio (SNDR) and most important of all, reduced sensitivity to analog imperfections.This thesis introduces several structures to overcome loop imperfections and stability issues in delta-sigma modulators. First, a new multi-loop delta-sigma modulator is proposed to combine the relaxed circuit requirements of single-loop modulators with the stability of traditional multi-loop modulators. Measurement results of the prototype IC confirmed with opamps with loop gain of less than 30dB, SNDR of over 74dB can be achieved. Also proposed is a new single-loop modulator using a delay-free two-step quantizer enabling the input signals beyond the full-scale range to be processed by the loop. The fabricated prototype IC achieves over 75dB SNDR by allowing signals up to +5dBFS input signals. Third, is a modified dual-slope ADC which achieves first-order quantization noise-shaping. Combined as the quantizer of a second-order delta-sigma loop, the fabricated prototype IC achieves third-order noise shaping with 78dB peak SNDR

A Brief Tutorial on Mixed Signal Approaches to Combat Electronic Counterfeiting

As integrated circuit (IC) designs become more and more complex, the globalization of the IC supply chain has become inevitable. Because multiple entities are required to design, fabricate, test, and distribute an IC, the need for reliable security and assurance methods to maintain trust throughout the entire supply chain has never been more critical. This tutorial introduces a variety of mixed-signal approaches to combat electronic counterfeiting. An LDO-based odometer capable of accurately classifying ICs as new or aged is presented as a promising method for detecting counterfeit and recycled ICs. Additionally, this tutorial discusses the use of physical unclonable functions (PUFs) as primitives for generating cryptographic keys for digital signatures, encryption, or authentication. The design process of all PUFs is introduced and the key characteristics and evaluation metrics of state-of-the-art PUFs are defined. Finally, to promote digital IP protection, several methods for camouflaged digital gates are presented and analyzed. The threshold voltage defined (TVD) logic families discussed are capable of implementing any N-to-1 logic function and are highly resilient to reverse engineering attacks

Using Compound Neural Action Potentials for Functional Validation of a High-Density Intraneural Interface: A Preliminary Study

Compound nerve action potentials (CNAPs) were used as a metric to assess the stimulation performance of a novel high-density, transverse, intrafascicular electrode in rat models. We show characteristic CNAPs recorded from distally implanted cuff electrodes. Evaluation of the CNAPs as a function of stimulus current and calculation of recruitment plots were used to obtain a qualitative approximation of the neural interface’s placement and orientation inside the nerve. This method avoids elaborate surgeries required for the implantation of EMG electrodes and thus minimizes surgical complications and may accelerate the healing process of the implanted subject

Intraneural active probe for bidirectional peripheral nerve interface

status: publishe

Development of an active high-density transverse intrafascicular micro-electrode probe

In this work, the development of an active high-density transverse intrafascicular microelectrode (hd-TIME) probe to interface with the peripheral nervous system is presented. The TIME approach is combined with an active probe chip, resulting in improved selectivity and excellent signal-to-noise ratio. The integrated multiplexing capabilities reduce the number of external electrical connections and facilitate the positioning of the probe during implantation, as the most interesting electrodes of the electrode array can be selected after implantation. The probe chip is packaged using thin-film manufacturing techniques to allow for a minimally invasive electronic package. Special attention is paid to the miniaturization, the mechanical flexibility and the hermetic encapsulation of the device. A customized probe chip was designed and packaged using a flexible, implantable thin electronic package (FITEP) process platform. The platform is specifically developed for making slim, ultra-compliant, implantable complementary metal-oxide-semiconductor based electronic devices. Multilayer stacks of polyimide films and HfO2/Al2O3/HfO2 layers deposited via atomic layer deposition act as bidirectional diffusion barriers and are key to the hermetic encapsulation. Their efficacy was demonstrated both by water vapor transmission rate tests and accelerated immersion tests in phosphate buffered saline at 60 °C. Using the hd-TIME probe, an innovative implantation method is developed to prevent the fascicles from moving away when the epineurium is pierced. In addition, by transversally implanting the hd-TIME probe in the proximal sciatic nerve of a rat, selective activation within the nerve was demonstrated. The FITEP process platform can be applied to a broader range of integrated circuits and can be considered as an enabler for other biomedical applications

FITEP : a Flexible Implantable Thin Electronic Package platform for long term implantation applications, based on polymer and ceramic ALD multilayers

Within our internal FITEP technology platform (FITEP: Flexible Implantable Thin Electronic Package), a novel implantable packaging technology is under development in order to realize a very small, flexible, biomimetic package for electronic implants. This new platform enables a radical miniaturization of the final implanted device, which opens many new possibilities for the medical world, since it will be possible to insert electronic sensors in very small locations, such as arteries, nerves, glands,... The device encapsulation consists of a multilayer of biocompatible polymers and ultrathin ceramic diffusion barriers deposited using ALD techniques (ALD: atomic layer deposition) in order to fabricate a very thin and flexible but also highly hermetic device packaging. Concerning the selection of biocompatible polymers, polyimide can offer a profound mechanical support for the various device components, while Parylene with its excellent step coverage creates a highly conformal coating surrounding all components. Hermeticity can be realized by the use of ultrathin ceramic ALD layers such as Al2O3 and HfO2. An optimized ALD process will result in layers from very high quality with very good step coverage. As such, selected ALD layers of only a few tens of nm thick, can exhibit very low Water Vapor Transmission Rates (WVTR), making these ALD materials ideal as ultrathin diffusion barriers. The tested polyimide/ALD stack proved to be a very hermetic enclosure: copper patterns protected with the polyimide/ALD stack are still in perfect condition after more than 2 years of immersion in saline at 60 °C (test is still ongoing), while Cu patterns protected by the polyimide stack without ALD barriers showed first signs of damage already after 6 weeks exposure to saline. Platinum and gold are best suited for metallization of implanted electronics, but these noble metals do not adhere easily to polymers, hence dedicated measures to promote metal-polymer adhesion are essential. The FITEP platform is applied on a Si-probe for implantation in the peripheral nerves, consisting of a CMOS chip with recording and stimulation electrodes [Op de Beeck, M. 2017]. The chip is thinned down to 35um and packaged using polyimide and ALD multi-stacks, resulting in a 75um thin fully encapsulated chip, optimized to reduce the Foreign Body Reaction to obtain optimum electrode-nerve contact. Flexible interconnects are fabricated using gold and platinum sandwiched between polymers and ALD layers. For optimal charge injection, iridium oxide is used as electrode material. After this hermetic FITEP-based chip encapsulation, the CMOS chip is still fully functional, which was tested dry (in air) as well as during submersion in saline. First acute in vivo stimulation tests have shown good electrode stimulation capabilities. Mechanical bending tests on long 5um thick gold interconnects are performed, showing that even after up to 1.5 million bending cycles, no cracks occurred in the gold patterns (testing in air). Longer term immersion in saline and in-vivo testing showed some problems related to loss of adhesion and to galvanic effects of the metallization. These observations were leading to some improvements in the fabrication of the encapsulation. In a second packaging iteration of the CMOS chip, these improvements were realized and a new series of encapsulated devices is fabricated. First results are promising, showing improved metal adhesion. Longer term stability tests are on its way