Modeling of thermally induced skew variations in clock distribution network

Clock distribution network is sensitive to large thermal gradients on the die as the performance of both clock buffers and interconnects are affected by temperature. A robust clock network design relies on the accurate analysis of clock skew subject to temperature variations. In this work, we address the problem of thermally induced clock skew modeling in nanometer CMOS technologies. The complex thermal behavior of both buffers and interconnects are taken into account. In addition, our characterization of the temperature effect on buffers and interconnects provides valuable insight to designers about the potential impact of thermal variations on clock networks. The use of industrial standard data format in the interface allows our tool to be easily integrated into existing design flow

Automated Segmentation of Cells with IHC Membrane Staining

This study presents a fully automated membrane segmentation technique for immunohistochemical tissue images with membrane staining, which is a critical task in computerized immunohistochemistry (IHC). Membrane segmentation is particularly tricky in immunohistochemical tissue images because the cellular membranes are visible only in the stained tracts of the cell, while the unstained tracts are not visible. Our automated method provides accurate segmentation of the cellular membranes in the stained tracts and reconstructs the approximate location of the unstained tracts using nuclear membranes as a spatial reference. Accurate cell-by-cell membrane segmentation allows per cell morphological analysis and quantification of the target membrane proteins that is fundamental in several medical applications such as cancer characterization and classification, personalized therapy design, and for any other applications requiring cell morphology characterization. Experimental results on real datasets from different anatomical locations demonstrate the wide applicability and high accuracy of our approach in the context of IHC analysi

A Software-based Low-Jitter Servo Clock for Inexpensive Phasor Measurement Units

This paper presents the design and the implementation of a servo-clock (SC) for low-cost Phasor Measurement Units (PMUs). The SC relies on a classic Proportional Integral (PI) controller, which has been properly tuned to minimize the synchronization error due to the local oscillator triggering the on-board timer. The SC has been implemented into a PMU prototype developed within the OpenPMU project using a BeagleBone Black (BBB) board. The distinctive feature of the proposed solution is its ability to track an input Pulse-Per-Second (PPS) reference with good long-term stability and with no need for specific on-board synchronization circuitry. Indeed, the SC implementation relies only on one co-processor for real-time application and requires just an input PPS signal that could be distributed from a single substation clock