SVX Sequence Crate Custom J2/J3 Backplane

The Custom J2/J3 Backplane is a full length (21 slot) user specified custom 3U backplane to be used in both the J2 and J3 positions. Slot spacing is identical to that used for VME (0.8-inch), and each backplane shall fit into a standard Eurocard VME style crate. The purpose of the Custom J2/J3 Backplane is to send and receive control and clock signals from the SVX chips via 3M pleated foil cables (Slots 2-21), and in slot 1, accept a cable connector and route its signal through to a signal distribution board

SVX Sequence Crate Custom J1 Backplane

The Custom J1 Backplane is a full length (21 slot) user specified custom 3U backplane to be used in the J1 position. Slot spacing is identical to that used for VME (0.8-inch), and each backplane shall fit into a standard Eurocard VME style crate. The purpose of the Custom J1 Backplane is to: (1) Provide +5 volt power to slots 1 through 21; (2) Provide -5.2 volt power to slots 1 through 21; (3) Provide five bits of geographic addressing to slots 2 through 21. Slot 2 will have all five bits pulled low; slot 21 will have the value 10100. See Appendix A; (4) Route a differential 1553 signal from a triaxial bulkhead connector to slots 2 through 11. This differential signal is bussed as a daisy chain. A 75 ohm resistor to ground shall be located near the last destination slot for each of these two signals; (5) Route a second differential 1553 signal from a triaxial bulkhead connector to slots 12 through 21. This differential signal is bussed as a daisy chain. A 75 ohm resistor to ground shall be located near the last destination slot for each of these two signals; (6) Route two NRZ signals and two Clock signals from slot 1 to each of slots 2 through 21. These are individual signals, not bussed

Long-term Running Experience with the Silicon Micro-strip Tracker at the D{\O} detector

The SiliconMicro-strip Tracker (SMT) at the D{\O} experiment in the Fermilab Tevatron collider has been operating since 2001. In 2006, an additional layer, referred to as 'Layer 0', was installed to improve impact parameter resolution and compensate for detector degradation due to radiation damage to the original innermost SMT layer. The SMT detector provides valuable tracking and vertexing information for the experiment. This contribution will highlight aspects of the long term operation of the SMT, including the impact of the silicon readout test-stand. Due to the full integration of the test-stand into the D{\O} trigger framework, this test-stand provides an advantageous tool for training of new experts and studying subtle effects in the SMT while minimizing impact on the global data acquisition.Comment: Proceedings of TIPP 2011 (Technology and Instrumentation for Particle Physics 2011), June 9-14 2011, Chicago, US

D0 Silicon Strip Detector Upgrade Project SVX Sequencer Controller Board

The Sequencer Controller boards are 9U by 340mm circuit boards that will reside in slot 1 of each of eight Sequencer crates in the D0 detector platform. The primary purpose is to control the Sequencers during data acquisition based on trigger information from the D0 Trigger Framework. Functions and features are as follows: (1) Receives the Serial Command Link (SCL) from the D0 Trigger System and controls the operation of the Sequencers by forming a custom serial control link (NRZ/Clock) which is distributed individually to each Sequencer via the 11 Backplane; (2) Controllable delays adjust NRZ control link phasing to compensate for the various cable-length delays between the Sequencers and SVX chips, delay control is common for slots 2-11, and for slots 12-21 of the crate; (3) Each NRZ control link is phase controlled so that commands reach each Sequencer in a given half-crate simultaneously, i.e., the link is compensated for backplane propagation delays; (4) External communication via MIL-STD-1553; (5) Stand-alone operation via 1553 trigger commands in absence of an SCL link; (6) 1553-writeable register for triggering a laser, etc. followed by an acquisition cycle; (7) TTL front panel input to trigger an acquisition cycle, e.g. from a scintillator; (8) Synch Trig, Veto, Busy and Preamp Reset TTL outputs on front panel LEMOs; (9) On-board 53.104 MHz oscillator for stand-alone operation; (10) 1553 or SCL-triggerable Cal-inject cycle; (11) Front-panel inputs to accept NRZ/Clock link from the VRB Controller; (12) Front panel displays and LEDs show the board status at a glance; and (13) In-system programmable EPLDs are programmed via Altera's 'Byteblaster'

Port Card Moduel

The Port Card will be one link in the data acquisition system for the D0 Silicon Vertex Detector. This system consists of the following parts, starting at the detector: Silicon strip detectors are mounted in a spaceframe and wire-bonded to custom bare-die integrated circuits (SVX-II chips) that digitize the charge collected by the strips. The 128-channel chips are mounted on a High-Density Interconnect (HDI) that consists of a small flex circuit that routes control signals and eight data bits for each of three to ten chips onto a common data bus. A cable then routes this bus approximately thirty feet out from the detector to the Port Card. The Port Card houses a commercial chipset that serializes the data in real time and converts the signal into laser light impulses that are then transmitted through a multi-mode optical fiber about 150 feet to a Silicon Acquisition & Readout board (SAR). Here, the data is transformed back to parallel electrical signals that are stored in one of several banks of FIFO memories. The FIFOs place their data onto the VME backplane to a VME Buffer Driver (VBD) which stores the event data in buffers for eventual readout over a thirty-two signal ribbon cable to the Level Two Computers and subsequent tape storage. Control and sequencing of the whole operation starts with the Silicon Acquisition/Readout Controller (SARC) working in tandem with the D0 Clock System. The SARC resides in the same VME crate as the SARs, and transforms signals from the Trigger System into control codes distributed to the various Port Cards via optical fibers operating at 53 Mb/s. It is through these control codes that data taking operations such as data-acquisition, digitization, readout, and various resets can be carried out. The Port Card receives the control codes and manipulates the SVX-II chips in the proper way to effect proper data taking. There will be a total of about 700,000 channels, which translates into about 5580 SVX-II chips, 66 to 100 Port Cards, 66 to 100 SARs, and four to eight SARCs

Architecture of a Silicon Strip Beam Position Monitor

A collaboration between Fermilab and the Institute for High Energy Physics (IHEP), Beijing, has developed a beam position monitor for the IHEP test beam facility. This telescope is based on 5 stations of silicon strip detectors having a pitch of 60 microns. The total active area of each layer of the detector is about 12x10 cm2. Readout of the strips is provided through the use of VA1` ASICs mounted on custom hybrid printed circuit boards and interfaced to Adapter Cards via copper-over-kapton flexible circuits. The Adapter Cards amplify and level-shift the signal for input to the Fermilab CAPTAN data acquisition nodes for data readout and channel configuration. These nodes deliver readout and temperature data from triggered events to an analysis computer over gigabit Ethernet links.Comment: Submitted to TWEPP 201

The Layer 0 Inner Silicon Detector of the D0 Experiment

This paper describes the design, fabrication, installation and performance of the new inner layer called Layer 0 (L0) that was inserted in the existing Run IIa Silicon Micro-Strip Tracker (SMT) of the D0 experiment at the Fermilab Tevatron collider. L0 provides tracking information from two layers of sensors, which are mounted with center lines at a radial distance of 16.1 mm and 17.6 mm respectively from the beam axis. The sensors and readout electronics are mounted on a specially designed and fabricated carbon fiber structure that includes cooling for sensor and readout electronics. The structure has a thin polyimide circuit bonded to it so that the circuit couples electrically to the carbon fiber allowing the support structure to be used both for detector grounding and a low impedance connection between the remotely mounted hybrids and the sensors.Comment: 28 pages, 9 figure

Design and construction of the MicroBooNE detector

This paper describes the design and construction of the MicroBooNE liquid argon time projection chamber and associated systems. MicroBooNE is the first phase of the Short Baseline Neutrino program, located at Fermilab, and will utilize the capabilities of liquid argon detectors to examine a rich assortment of physics topics. In this document details of design specifications, assembly procedures, and acceptance tests are reported