FPGA Implementation of UFMC based baseband transmitter: case study for LTE 10MHz channelization

Universal filtered multicarrier (UFMC) is a low complexity promising waveform that provides quasi-orthogonal property among subcarriers. In addition, it can achieve much better out-of-band emission performance than orthogonal frequency division multiplexing (OFDM) system. Authors have proposed a hardware platform to implement a UFMC transmitter in this paper. Highly reduced complexity schemes for IFFT, filtering, and spectrum shifting are realized on actual hardware. This helps to achieve overall architecture of the transmitter at the cost of minimal FPGA resource usage. Hence, the overall design uses only 1038 slice registers, 1154 slice LUTs, and 64 multipliers of Xilinx Virtex-7 XC7VX330t device. A throughput of 773.5 Msamples/sec at an operational frequency of 364 MHz is achieved. This throughput is adequate for processing 50 Physical Resource Blocks (PRB) of LTE 10 MHz channelization in required time. The presented architecture provides a latency of only 2% of one LTE 10MHz channelization symbol due to the implementation of pipelining at different levels. Although the presented hardware design in its current form meets LTE 10MHz channelization throughput requirements, further increase in throughput is possible due to the scalable nature of the architecture. To the best of our knowledge, this work is first ever FPGA solution for UFMC transmitter presented in the literature

PANC Study (Pancreatitis: A National Cohort Study): national cohort study examining the first 30 days from presentation of acute pancreatitis in the UK

Abstract Background Acute pancreatitis is a common, yet complex, emergency surgical presentation. Multiple guidelines exist and management can vary significantly. The aim of this first UK, multicentre, prospective cohort study was to assess the variation in management of acute pancreatitis to guide resource planning and optimize treatment. Methods All patients aged greater than or equal to 18 years presenting with acute pancreatitis, as per the Atlanta criteria, from March to April 2021 were eligible for inclusion and followed up for 30 days. Anonymized data were uploaded to a secure electronic database in line with local governance approvals. Results A total of 113 hospitals contributed data on 2580 patients, with an equal sex distribution and a mean age of 57 years. The aetiology was gallstones in 50.6 per cent, with idiopathic the next most common (22.4 per cent). In addition to the 7.6 per cent with a diagnosis of chronic pancreatitis, 20.1 per cent of patients had a previous episode of acute pancreatitis. One in 20 patients were classed as having severe pancreatitis, as per the Atlanta criteria. The overall mortality rate was 2.3 per cent at 30 days, but rose to one in three in the severe group. Predictors of death included male sex, increased age, and frailty; previous acute pancreatitis and gallstones as aetiologies were protective. Smoking status and body mass index did not affect death. Conclusion Most patients presenting with acute pancreatitis have a mild, self-limiting disease. Rates of patients with idiopathic pancreatitis are high. Recurrent attacks of pancreatitis are common, but are likely to have reduced risk of death on subsequent admissions. </jats:sec

RCIA: A New Ultralightweight RFID Authentication Protocol Using Recursive Hash

RFID is one of the most protuberant systems in the field of ubiquitous computing. Since RFID tags have limited computation capabilities, numerous ultralightweight authentication protocols have been proposed to provide privacy and security. However all the previously proposed ultralightweight mutual authentication protocols have some security apprehensions and are vulnerable to various desynchronization and full disclosure attacks. This paper proposes a new ultralightweight mutual authentication protocol to provide robust confidentiality, integrity, and authentication (RCIA) in a cost effective manner. RCIA introduces a new ultralightweight primitive recursive hash, which efficiently detects the message tempering and also avoids all possible desynchronization attacks. RCIA involves only bitwise operations such as XOR, AND, left rotation, and recursive hash. Performance evaluation illustrates that RCIA requires less resources on tag in terms of on-chip memory, communication cost, and computational operations

Refractivity variations and propagation at Ultra High Frequency

Present framework is established to deal with the refractivity variations normally affected the radio waves propagation at different frequencies, ranges and different environments. To deal such kind of effects, many researchers proposed several methodologies. One method is to use the parameters from meteorology to investigate these effects of variations in refractivity on propagation. These variations are region specific and we have selected a region of one kilometer height over the English Channel. We have constructed different modified refractivity profiles based on the local meteorological data. We have recorded more than 48 million received signal strength from a communication links of 50 km operating at 2015 MHz in the Ultra High Frequency band giving path loss between transmitting and receiving stations of the experimental setup. We have used parabolic wave equation method to simulate an hourly value of signal strength and compared the obtained simulated loss to the experimental loss. The analysis is made to compute refractivity distribution of standard (STD) and ITU (International Telecommunication Union) refractivity profiles for various evaporation ducts. It is found that a standard refractivity profile is better than the ITU refractivity profiles for the region at 2015 MHz. Further, it is inferred from the analysis of results that 10 m evaporation duct height is the dominant among all evaporation duct heights considered in the research. Keywords: Refractive index, Refractivity, Parabolic wave equation, Propagation, UHF, Antenna

A New Ultralightweight RFID Mutual Authentication Protocol: SASI Using Recursive Hash

RFID is one of the most prominent identification schemes in the field of pervasive systems. Nonline of sight capability makes RFID systems much better choice than its contended systems (such as barcode, magnetic tape, etc.). Since the RFID uses wireless channel for communication with its associated devices, there should be some optimal encryption methods to secure the communicating data from adversaries. Several researchers have proposed ultralightweight mutual authentication protocols (UMAPs) to secure the RFID systems in cost effective manner. Unfortunately most of the previously proposed UMAPs are later found to be vulnerable against various desynchronization, Denial of Service (DoS), traceability, and full disclosure attacks. In this paper, we present a more sophisticated UMAP to provide Strong Authentication and Strong Integrity (SASI) using recursive hash function. The proposed protocol incorporates only simple bitwise logical operators XOR, Rot, and nontriangular function (recursive hash) in its design, which can be efficiently implemented with a low cost passive RFID tag. The performance analysis of the protocol proves the conformation of the proposed protocol with EPC-C1G2 passive tags. In addition to privacy and security, small chip area (miniaturization) is another design constraint (which is mandatory requirement for a protocol to be considered as ultralightweight authentication protocol). We have also proposed and implemented the efficient hardware design of the proposed protocol for EPC-C1G2 tags. Both the FPGA and ASIC implementation flows have been adopted. The FPGA flow is primarily used to validate the functionality of the proposed hardware design whereas ASIC flow (using TSMC 0.35  μ m library) is used to validate the gate count. To the best of our knowledge, this is the first FPGA and ASIC implementation of any ultralightweight RFID authentication protocol

Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations Demapper

International audienc

Auto implementation of parallel hardware architecture for Aho-Corasick algorithm

Pattern matching using Aho-Corasick (AC) algorithm is the most time-consuming task in an Intrusion Detection System, and therefore, the Field Programmable Gate Array (FPGA) based solutions are frequently employed. In this context, the two possibilities are memory based solutions and hardwired solution. The limitation of memory based solutions is the inefficient utilization of slices while the hardwired solutions require a tremendous amount of effort and time as writing Hardware Description Language (HDL) code for thousands of rules is prone to human errors. Consequently, the contributions of this article are twofold. The first contribution is to develop a tool for the automatic generation of Verilog-HDL code from the rule set. The second contribution is to propose an efficient parallel hardware implementation scheme and compare it with a serial hardware implementation scheme in terms of various design parameters such as resource utilization, operational frequency and throughput. The proposed parallel scheme advocates the division of entire rule set into smaller sub-sets for parallel execution. Experimental results reveal that the proposed tool can generate the target code for 10,000 rules in less than a minute without any error. The automatic generation of target code has allowed to perform a comprehensive design space exploration for the parallel implementation of AC algorithm in quick time. Finally, our Xilinx ZC702 evaluation FPGA board based prototype for 10,000 rules can efficiently examine the packet stream coming at a bit rate of 1.56 Gbps at an operational frequency of 195 MHz

Hardware complexity reduction in universal filtered multicarrier transmitter implementation

The inclusion of machine-type communication in the 5G technology has motivated the research community to explore new derivative waveforms of orthogonal frequency division multiplexing. Filter bank multicarrier, universal filtered multicarrier (UFMC), and generalized frequency division multiplexing techniques are under evaluation with respect to their suitability to 5G requirements. In addition to acceptable spectral performance, investigation on computational complexity reduction while addressing flexibility can help in the selection of suitable waveform among multiple options available for 5G. In this regard, based on analysis of computation involved in UFMC waveform construction, few reduced complexity solution for UFMC transmitter implementations are recently proposed. However, hardware-implementation-related issues have not been discussed in detail. In this paper, we have proposed reduced complexity hardware solutions for all three constituent blocks, i.e., inverse discrete Fourier transform (IDFT), finite impulse response (FIR) filter, and spectrum shifting blocks of a UFMC transmitter. For IDFT part, a reduced complexity IFFT solution using Radix-2 decimation in a time technique is presented, where more than 42% computations can be avoided. It is also shown that how five times less number of multipliers can be used in an FIR filter to simplify filter architecture. Finally, a highly efficient method is presented to compute spectrum shifting coefficients through small sized lookup table