A model to explain angular distributions of J/ψJ/\psi and ψ(2S)\psi(2S) decays into ΛΛ‾\Lambda\overline{\Lambda} and Σ0Σ‾0\Sigma^0\overline{\Sigma}^0

BESIII data show a particular angular distribution for the decay of the $J/\psi$ and $\psi(2S)$ mesons into the hyperons $\Lambda\overline{\Lambda}$ and $\Sigma^0\overline{\Sigma}^0$. More in details the angular distribution of the decay $\psi(2S) \to \Sigma^0\overline{\Sigma}^0$ exhibits an opposite trend with respect to that of the other three channels: $J/\psi \to \Lambda\overline{\Lambda}$, $J/\psi \to \Sigma^0\overline{\Sigma}^0$ and $\psi(2S) \to \Lambda\overline{\Lambda}$. We define a model to explain the origin of this phenomenon.Comment: 6 pages, 7 figures, to be published in Chinese Physics

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

PARSIFAL: a toolkit for triple-GEM parametrized simulation

PARSIFAL (PARametrized SImulation) is a tool which reproduces a triple-GEM detector full response to the passage of a charged particle, taking into account most of the involved physical effects. A triple-GEM is a gaseous detector that amplifies the primary ionization, generated by the incoming radiation interacting with the gas, through three amplification stages, providing position measurement with a resolution around 100 micron, energy resolution better than 20% and time resolution below 10 ns. Despite well known and robust software such as GARFIELD++ can simulate the electron propagation in gas and the interaction with the electric field, considering the avalanche formation and signal creation, they are CPU-time consuming. The necessity to reduce the processing time while maintaining the precision of a full simulation is the main driver of this work. PARSIFAL takes into account the main processes involved in the signal formation, starting from ionization, spatial and temporal diffusion, the effect of the magnetic field, if any, and GEM amplification properties. The induction of the signal and the electronics response are also present. PARSIFAL parameters are evaluated by means of GARFIELD++ simulations; the results of the simulation are compared to experimental data from testbeam and tuning factors are applied to improve the matching.Comment: submitted to JINS

A new inner tracker based on GEM detectors for the BES III experiment

A new inner tracker based on a cylindrical gas electron-multiplier detector is under development to replace the current inner drift chamber of the BES III spectrometer. The BES III experiment is carried out at the BEPC II e[Formula: see text]e[Formula: see text] collider in Beijing at center-of-mass energies in the tau-charm region with a design luminosity of 1.0 [Formula: see text] 10[Formula: see text] cm[Formula: see text]s[Formula: see text]. The new inner tracker consists of three cylindrical layers of triple GEM surrounding the interaction point, covering 93% of solid angle. To fulfill physics requirements, a spatial resolution of 130 μm must be achieved. Both planar and cylindrical prototypes have been built and tested. A custom ASIC using UMC 110-nm technology has been designed to provide charge and time measurements—the first prototype is in testing. Notable and innovative aspects of the new inner tracker and the performance of the detector prototypes and readout ASIC are reported here

Track-based alignment for the BESIII CGEM detector in the cosmic-ray test

The Beijing Electron Spectrometer III (BESIII) is a multipurpose detector operating on the Beijing Electron Positron Collider II (BEPCII). After more than ten year's operation, the efficiency of the inner layers of the Main Drift Chamber (MDC) decreased significantly. To solve this issue, the BESIII collaboration is planning to replace the inner part of the MDC with three layers of Cylindrical triple-Gas Electron Multipliers (CGEM). The new features of the CGEM detector will improve the spatial resolution to 130 $\mu$m. To meet this goal, a careful calibration of the detector is necessary to fully exploit the potential of the CGEM detector. In all the calibrations, the detector alignment plays an important role to improve the detector precision. The track-based alignment for the CGEM detector with the Millepede algorithm is implemented to reduce the uncertainties of the hit position measurement. Using the cosmic-ray data taken in 2020 with the two layers setup, the displacement of the outer layer with respect to the inner layer is determined by a simultaneous fit applied to more than 160000 tracks. A good alignment precision has been achieved that guarantees the design request could be satisfied in the future. A further alignment will be performed using the combined information of tracks from cosmic-ray and collisions after the CGEM is installed into the BESIII detector