Prospects for logic-on-a-wire

In this paper we present the top-down fabrication of gate-all-around (GAA) and body-tied @W-gate devices by a combination of etching and oxidation steps resulting in a local silicon-on-insulator structure. The GAA has advantages in terms of enhanced current drive, whereas the body-strapped structures allow for active leakage control and in some cases impact ionization devices. We demonstrate an inverter fabricated along a single silicon rib. The inverter consists of two enhancement mode body-strapped @W-gate NMOS transistors. Static and dynamic experiments demonstrate a fully functional inverter with the output experiencing V"D"D/2 voltage swing, as expected for an NMOS inverter with identical driver and load dimensions. In addition, we propose the use of these devices for cross-bar memory addressing

Advances, Challenges and Opportunities in 3D CMOS Sequential Integration

3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices. Finally, the development of a stable salicide enables to retain bottom performance after top FET processing. Overcoming these major technological issues offers a wide range of applications

Reliable Circuit Design with Nanowire Arrays

The emergence of different fabrication techniques of silicon nanowires (SiNWs) raises the question of finding a suitable architectural organization of circuits based on them. Despite the possibility of building conventional CMOS circuits with SiNWs, the ability to arrange them into regular arrays, called crossbars, offers the opportunity to achieve higher integration densities. In such arrays, molecular switches or phase-change materials are grafted at the crosspoints, i.e., the crossing nanowires, in order to perform computation or storage. Given the fact that the technology is not mature, a hybridization of CMOS circuits with nanowire arrays seems to be the most promising approach. This chapter addresses the impact of variability on the nanowires in circuit designs based on the hybrid CMOS-SiNW crossbar approach

FPGA Design with Double-Gate Carbon Nanotube Transistors

International audienc

RF characterization of the substrate coupling noise between TSV and active devices in 3D integrated circuits

International audienc