ALGORITMO DE PROCESAMIENTO DE DATOS PARA SENSORES DE FUERZA RESISTIVOS (DATA PROCESSING ALGORITHM FOR RESISTIVE FORCE SENSORS)

Resumen En este trabajo se presenta un algoritmo de procesamiento de datos y una interfaz de usuario para sensores de fuerza resistivos en un rango de baja presión, con el objetivo principal de implementarse en nuevos dispositivos resistivos. El algoritmo se desarrolló en el software LabVIEW debido a las funcionalidades que posee y su compatibilidad con múltiples tarjetas de adquisición de datos disponibles en el mercado; así mismo, permite la modificación de la ecuación característica del sensor de prueba, por lo que podría adaptarse a diferentes sensores de fuerza resistivos. Se presentan los resultados obtenidos de un sensor de fuerza resistivo comercial FSR406 utilizando diferentes niveles de calibración en la etapa de acondicionamiento de la señal, junto con un dispositivo de adquisición de datos NI-USB 6008 que posee compatibilidad directa con el software utilizado por comunicación serial. Palabras Clave: Algoritmo, Fuerza, Interfaz, LabVIEW, Sensor. Abstract In this work a data processing algorithm and a user interface for resistive force sensors in a low-pressure range are presented with the main objective of implementation in new resistive devices. The algorithm was developed in LabVIEW software due to its functionalities and its compatibility with multiple data acquisition boards available on the market; as well as allowing the modification of the characteristic equation of the test sensor, thus adapting to different resistive force sensors. The results obtained from a commercial FSR406 resistive force sensor using different calibration levels in the signal conditioning stage are presented together with an NI-USB 6008 data acquisition device that has direct compatibility with the software used for serial communication. Keywords: Algorithm, force, interface, LabVIEW, sensor

Compensation of third-order dispersion in a 100Gb/s single channel system with in-line fibre Bragg gratings

This paper presents a scheme to enhance the performance of an ultrahigh capacity(100 Gb/s) long haul transmission system that makes use of chirped fibre Bragggratings (FBG) for dispersion slope compensation. It is shown that the FBGeffectively compensate the dispersion slope while at the same time providingappropriate in-line filtering. The penalty to the system performance due tounwanted group delay ripple is also discussedPostprint (published version

Two New Asymmetric Boolean Chaos Oscillators with No Dependence on Incommensurate Time-Delays and Their Circuit Implementation

This manuscript introduces two new chaotic oscillators based on autonomous Boolean networks (ABN), preserving asymmetrical logic functions. That means that the ABNs require a combination of XOR-XNOR logic functions. We demonstrate analytically that the two ABNs do not have fixed points, and therefore, can evolve to Boolean chaos. Using the Lyapunov exponent’s method, we also prove the chaotic behavior, generated by the proposed chaotic oscillators, is insensitive to incommensurate time-delays paths. As a result, they can be implemented using distinct electronic circuits. More specifically, logic-gates–, GAL–, and FPGA–based implementations verify the theoretical findings. An integrated circuit using a CMOS 180nm fabrication technology is also presented to get a compact chaos oscillator with relatively high-frequency. Dynamical behaviors of those implementations are analyzed using time-series, time-lag embedded attractors, frequency spectra, Poincaré maps, and Lyapunov exponents

CMOS Analog Filter Design for Very High Frequency Applications

A design strategy for the synthesis of high-selectivity/low-order analog filters in Complementary Metal-Oxide-Semiconductor (CMOS) technology for very high frequency (VHF) applications is presented. The methodology for the reconstitution of a given transfer function by means of Signal Flow Graphs (SFG) manipulation in canonical form is proposed leading to a fully differential g m -C biquad filter. As a practical example, the design of a notch filter intended to suppress interferers in the lower sideband (400 MHz) of the Medical Implant Communication Service (MICS), in single-poly, 6-metal layers; Mixed-Signal/RF 0.18 µm CMOS technology is realized. To compare the performance of the proposal with some other solution, the design of a 7th order elliptic notch filter based on Frequency Dependent Negative Resistors (FDNRs) was also accomplished. The attained simulation results prove that the proposal is competitive compared to the FDNR solution and some other state-of-the-art filters reported in the literature. The most salient features of the proposed notch biquad include: the selectivity, whose value is comparable to that of a 7th order elliptic approach and some other 3rd order filters; a high-frequency operation without resonators; linearity, with a +15 dBm I I P 3 ; a reduced form factor with a total occupied area of 0.004282 mm2 and mostly a low design complexity