ULV and ULP active-RC filters combining single-stage OTA and negative input transconductance for low energy RF receivers.

Este trabalho propõe novas topologias de circuitos e técnicas de projeto para filtros ativos e amplificadores de ganho programável (PGA) com operação em ultra baixa tensão (ULV) e ultra-baixa potência (ULP). Os receptores de RF do tipo Bluetooth de baixa energia (BLE), utilizados nos circuitos de internet das coisas (IoT), são as aplicações alvo dos circuitos propostos neste trabalho. Na faixa de ULV são utilizados filtros do tipo RC-ativo, uma vez que possuem uma maior linearidade em relação aos filtros do tipo gmC. A operação em ULP é alcançada neste trabalho utilizando uma nova topologia de amplificador operacional de transcondutância (OTA), com único estágio, que apresenta uma alta eficiência e reduzida sensibilidade às variações de processo, tensão e temperatura (PVT). O baixo ganho de tensão do amplificador de estágio único e os efeitos das cargas resistivas de realimentação são compensados usando um transcondutor negativo, robusto a variações em PVT, conectado às entradas do OTA. A faixa dinâmica dos circuitos é elevada usando topologias totalmente diferenciais e as taxas de rejeição de modo comum e de fonte de alimentação são melhoradas utilizando circuitos de realimentação de modo-comum. Para possibilitar a operação na faixa de ULV todos os circuitos usam apenas dois transistores empilhados e o nível de inversão do canal é elevado através da polarização direta do substrato. Neste trabalho são propostas também uma ferramenta de análise do ponto de operação do transistor, baseando-se na simulação elétrica, e algumas metodologias de projetos para circuitos operando em ULV. Os circuitos e metodologias desenvolvidos foram utilizados para o projeto de um filtro passa-faixa complexo RC-ativo de terceira ordem, um amplificador de ganho programável e um filtro biquadrático do tipo Tow-Thomas com ganho programável, compatíveis com receptores de RF do padrão BLE. Para a implementação do PGA, uma nova topologia de transconductor negativo programável foi desenvolvida para permitir a compensação ótima do amplificador operacional em todos os modos de ganho. Todos os circuitos foram projetados para operar com uma tensão de alimentação de 0,4 V e foram prototipados em processos de fabricação CMOS e BiCMOS de 180 nm e 130 nm, respectivamente. Os resultados experimentais e de simulação pós-layout demonstram uma operação adequada em 0,4 V, uma ultra-baixa dissipação de potência, atingindo o mínimo de 10.9 ?W/polo, e a melhor figura-de-mérito (FoM) em relação aos outros filtros ativos e amplificadores disponíveis na literatura.This thesis proposes novel circuit topologies and design techniques of ultra-low voltage (ULV) and ultra-low power (ULP) active-filters and programmable gain amplifiers (PGA) suitable for the Bluetooth low energy (BLE) RF receivers used in the Internet of Things (IoT) applications. The active-RC filters are preferred to the gm-C topologies at the ULV operation due to its improved linearity. However, the closed-loop operation increases the operational amplifier required voltage gain and its capacity to drive the resistive feedback load. In this work, the ULP dissipation is obtained by proposing a very efficient single-stage inverter-based operational transconductance amplifier (OTA) and a proper forward bulk biasing to reduce the sensitivity to process, voltage and temperature (PVT) variations. The low voltage gain and the resistive load effects on the single-stage OTA are completely compensated by using a PVT robust negative transconductor connected at the OTA inputs. The dynamic range is increased by using fully-differential topologies and common-mode feedback to improve the common-mode and power supply rejection rates. The operation at the ULV range is reached by using only two-stacked transistors in all the circuit implementations and bulk forward bias in some transistors to reduce the threshold voltage and to increase the channel inversion level. An operation point simulation-based tool and some design methodologies are also proposed in this work to design the ULV circuits. The proposed circuits were used to design a third-order active-RC complex band-pass filter (CxBPF), a programmable gain amplifier (PGA) and a Tow-Thomas biquad, with integrated programmable gain capability, suitable for BLE RF receivers. The PGA implementation uses a new programmable input negative transconductor to obtain the optimal closed-loop amplifier compensation in all the gain modes. The circuits were designed to operate at the power supply voltage of 0.4 V and are prototyped in 180 nm and 130 nm low-cost CMOS and BiCMOS process, respectively. The experimental and post-layout simulation results have demonstrated the proper ULV operation at 0.4 V, the ultra-low power dissipation down to 10.9 ?W/pole and the best figure-of-merit (FoM) among the state-of-the-art active-filters and amplifiers from the literature

A Review on Vibration Monitoring Techniques for Predictive Maintenance of Rotating Machinery

Machine failure in modern industry leads to lost production and reduced competitiveness. Maintenance costs represent between 15% and 60% of the manufacturing cost of the final product, and in heavy industry, these costs can be as high as 50% of the total production cost. Predictive maintenance is an efficient technique to avoid unexpected maintenance stops during production in industry. Vibration measurement is the main non-invasive method for locating and predicting faults in rotating machine components. This paper reviews the techniques and tools used to collect and analyze vibration data, as well as the methods used to interpret and diagnose faults in rotating machinery. The main steps of this technique are discussed, including data acquisition, data transmission, signal processing, and fault detection. Predictive maintenance through vibration analysis is a key strategy for cost reduction and a mandatory application in modern industry

ASIPAMPIUM: An Efficient ASIP Generator for Low Power Applications

The adoption of customized ASIPs (Application Specific Instruction Set Processors) in embedded circuits is an important alternative for optimizing power consumption, silicon area, or processing performance according to the design requirements. The processor is implemented specifically for the target application, which allows the hardware customization in terms of instruction set architecture, data word length, memory size, and parallelism. This work describes an EDA tool for the semi-automatic development of ASIPs named ASIPAMPIUM. The strategy is to provide a set of integrated tools to interpret and generate a customized hardware for a given target application, including compilation, simulation, and hardware synthesis. From the C code description of the application, the tool returns a synthesizable hardware description of the processor. The proposed methodology is based on the adaptation of a new customizable microprocessor called PAMPIUM, which can be optimized in terms of silicon area, power consumption, or processing performance according to the target application. The ASIPAMPIUM tool provides a series of simulated data to the designer in order to identify optimization strategies in both software and hardware domains. We show the results for the implementation of an FFT algorithm using the proposed methodology, which achieved best results in terms of silicon area and energy consumption compared to other works described in the literature for both FPGA and silicon implementation. Moreover, measurement results of the implementation in silicon of a dedicated ASIP for interfacing with six sensors in real-time, including three I2C, an SPI, and an RS-232 interfaces, demonstrate the complete design flow, from the C code program to physical implementation and characterization. Aside from providing a short design time, the ASIPAMPIUM tool also affords a simple and intuitive design flow, allowing the designer to deal with different design trade-offs and objectives