An Efficient FPGA parallel Architecture for H.264/AVC Intra Prediction Algorithm

International audienceIn Motion Picture Experts Group (MPEG) and Video Coding Experts Group (VCEG) standards, intra prediction is used to eliminate the spatial redundancy. Given that the intra prediction stage is very complex in terms of computational effort, a hardware implementation on a re-configurable circuit is crucial for the requirements of different real-time multimedia applications. In this paper, we present novel hardware architecture for real-time implementation of intra prediction algorithm used in H.264 Advanced Video Coding (AVC) baseline profile video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for videoconference applications. We use an approach based on a novel organization of the intra prediction equations. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. On ALTERA Stratix II FPGA, the VHDL code is verified to work at 300 MHz for the luma intra prediction 4x4 architecture and 176 MHz for the luma intra prediction 16x16

Hardware architecture for H.264/AVC deblocking filter algorithm

International audienceThis paper presents novel hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264/AVC baseline profile video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. We use a novel edge filter ordering in a Macroblock to prevent the deblocking filter hardware from unnecessarily waiting for the pixels that will be filtered become available. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. The VHDL code is verified to work at 150 MHz in an ALTERA Stratix II FPGA

FPGA DESIGN FOR H.264/AVC ENCODER

International audienceIn this paper, we describe an FPGA H.264/AVC encoder architecture performing at real-time. To reduce the critical path length and to increase throughput, the encoder uses a parallel and pipeline architecture and all modules have been optimized with respect the area cost. Our design is described in VHDL and synthesized to Altera Stratix III FPGA. The throughput of the FPGA architecture reaches a processing rate higher than 177 million of pixels per second at 130 MHz, permitting its use in H.264/AVC standard directed to HDTV

An optimized and unified architecture design for H.265/HEVC 1-D inverse core transform

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An efficient and unified 2D-inverse integer cosine transform (IICT) FPGA-hardware implementation for HEVC standard

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An efficient pipeline execution of H.264/AVC intra 4×4 frame design

International audienceIn this paper, we present an implementation of an optimized H.264 intra 4 × 4 algorithm in order to reduce the time of the intra 4 × 4 process. However the source of waste time in conventional architecture of intra 4 × 4 is the serialization of intra prediction and reconstruction of sixteen 4 × 4 blocks in one macroblock and the intra prediction of the current 4 × 4 block cannot be performed before the reconstruction of the previous 4 × 4 block. Therefore, for a high speed implementation we replaced the conventional one by a pipelined architecture while maintaining consistency with the standard. So we have studied ten alternative scanning orders based on rearranging order of intra 4 × 4 and we choose the best one which reduce dependencies between consecutively executed blocks without performance degradation. This order is implemented by a pipelined architecture using VHDL language. The VHDL code is verified to work at 100 MHz in an ALTERA Stratix II EP2S60F1020C3 FPGA. As a result, the processing time is reduced by 31.25% compared to the conventional implementation. So, it can be a good solution for real-time video application. The H.264 intra 4 × 4 hardware and software are demonstrated to work together on ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA

Impact of varying processor number for H264 in FPGA platform

International audienceMultiprocessor architecture can be a solution to meet the increasing computational requirements for multimedia treatment algorithms such as video encoding. In this paper we study the effect of varying the processors number on resource utilization and system performance. We used Altera's NIOS II processors interconnected through Avalon bus. We vary the processors number from one to four and note its effect on the use of logic elements, DSP blocks and memory bits. We also note the change of the time execution of the Intra 16×16 chain of the H264/AVC encoder

Hardware implementation and validation of the fast variable block size motion estimation architecture for H.264/AVC

International audienceBlock matching motion estimation is the heart of video coding system. It leads to a high compression ratio, whereas it is time consuming and calculation intensive. Many fast search block matching motion estimation algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. In this paper, we propose an efficient hardware architecture of the fast line diamond parallel search (LDPS) algorithm with variable block size motion estimation (VBSME) for H.264/AVC video coding system. The design is described in VHDL language, synthesized to Altera Stratix III FPGA and to TSMC 0.18 m standard-cells. The throughput of the hardware architecture reaches a processing rate up to 78 millions of pixels per second at 83.5 MHz frequency clock and uses only 28 kgates when mapped to standard-cells. Finally, a system on a programmable chip (SoPC) implementation and validation of the proposed design as an IP core is presented using the embedded video system

AN EFFICIENT ARCHITECTURE VLSI FOR 4×4 INTRA PREDICTION IN HEVC STANDARD

International audienceThe HEVC is a proposal of new video coding standard that will be used for a wide range of applications like ULTRA HD and 3D applications. MPEG and VCEG have established a Joint Collaborative Team on Video Coding (JCT-VC) to develop the HEVC (High Efficiency Video Coding) standard which is expected to provide a significant improvement in data transmission and streaming efficiency compared to H.264. In this proposal standard, various modules of coding are defined. Among the most complex is the module of the intra prediction. The HEVC defines 35 modes of intra prediction for 8 × 8, 16 × 16, 32 × 32, 3 modes for 64 × 64 and 17 modes for 4 × 4 while the H.264/AVC (Advanced Video Coding) uses 9 modes for intra 4 × 4 and 4 modes for intra 16 × 16. In this paper, we propose an efficient uniform architecture for all of the 4 × 4 intra directional modes. This architecture offers an important gain in case of treatment time compared to the literature. Our proposed architecture is implemented with the technology TSMC 0.18μm CMO

A new hardware architecture of the adaptive vector median filter and validation in a hardware/software environment

International audiencePresented in this paper is a new hardware architecture of the adaptive vector median filter (AVMF). The suggested structure yielded important values in impulsive noise removal from color images while preserving their fine details. The software (SW) study of this filter demonstrated that its implementation is too complex. To overcome this limitation, some approximations using a ROM memory were proposed to perform the square root for a hardware (HW) implementation. Comparative results between the ideal and approximated SWs of the AVMF showed a relative error equal to 0.01%. Then, sequential and parallel HW architectures were developed for this filter based on the approximated method. Finally, the validation of these architectures was conducted using an field-programmable gate array (FPGA) platform on an HW/SW environment. The validation results demonstrated that the proposed HW/SW implementation of the AVMF can speed up the execution time 180 times in the worst case at 140 MHz compared to the SW solution as well as preserving a high data quality (same image quality)