Highly sensitive protection scheme considering the PV operation control models

The integration of distributed generation (DG) based on inverters into power systems has increased significantly, necessitating a thorough understanding of its impact on fault analysis and the performance of distribution networks' protection mechanisms. This study addresses this issue by examining how various inverter management modes influence protective relay systems within IEEE 9-bus redial and mesh networks, CIGRE and IEEE 33-bus networks featuring Photovoltaic (PV) farms and Battery Energy Storage Systems (BESS), by IEEE1547–2018 and German grid code standards. By analyzing grid-connected scenarios with five distinct PV control modes, the research introduces a novel protection methodology termed the Photovoltaic Overcurrent Relay (PVOCR). This method introduces a current-voltage characteristic to optimally coordinate Overcurrent Relays (OCRs), aiming to reduce their operational time and eliminate mis-coordination events. The proposed PVOCR is evaluated against standard inverse time, SOCR, and modern adaptive voltage, VOCR, relay schemes across various fault scenarios differing in type and location. Furthermore, the PVOCR scheme effectively operates across all PV inverter modes without experiencing miscoordination events, whereas the SOCR and VOCR schemes encountered such issues during the operation of Control 4. These results underscore the potential utility of the PVOCR methodology in enhancing the reliability and efficiency of protection systems in inverter-based DG networks

Innovative protection schemes through hardware-in-the-loop dynamic testing.

In microgrid environments, the behaviour of Distributed Generation (DG) during fault conditionsvaries significantly based on DG types and penetration levels. Conventional Overcurrent Relays(OCRs) with standard time-current characteristics may exhibit limitations during excessive faultscenarios, leading to OCR operating delays and mis-coordination within the microgrid. This studyproposes a novel constraint on the maximum Current Multiplier Setting (CMS) and utilizes WaterCycle Algorithm (WCA) and Particle Swarm Optimization (PSO) techniques to optimize the TimeMultiplier Setting (TMS). Comparative dynamic analysis through real-time validation shows thatthe non-standard OCR approach outperforms the standard IEC scheme across all grid operationmodes with different type, size and location of DGs. For instance, under F1 conditions, thetripping time of OCR1 was reduced from 0.0226 seconds (IEC) to 0.000981 seconds (non-stan-dard). HIL results further affirm the efficacy of the proposed scheme. The optimization process,implemented in MATLAB and validated using ATP/EMTP simulations and SIPROTEC 7SJ62 re-lays, demonstrates enhanced microgrid protection coordination, improving system reliability andperformance

An Efficient FPGA parallel Architecture for H.264/AVC Intra Prediction Algorithm

International audienceIn Motion Picture Experts Group (MPEG) and Video Coding Experts Group (VCEG) standards, intra prediction is used to eliminate the spatial redundancy. Given that the intra prediction stage is very complex in terms of computational effort, a hardware implementation on a re-configurable circuit is crucial for the requirements of different real-time multimedia applications. In this paper, we present novel hardware architecture for real-time implementation of intra prediction algorithm used in H.264 Advanced Video Coding (AVC) baseline profile video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for videoconference applications. We use an approach based on a novel organization of the intra prediction equations. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. On ALTERA Stratix II FPGA, the VHDL code is verified to work at 300 MHz for the luma intra prediction 4x4 architecture and 176 MHz for the luma intra prediction 16x16

Hardware architecture for H.264/AVC deblocking filter algorithm

International audienceThis paper presents novel hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264/AVC baseline profile video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. We use a novel edge filter ordering in a Macroblock to prevent the deblocking filter hardware from unnecessarily waiting for the pixels that will be filtered become available. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. The VHDL code is verified to work at 150 MHz in an ALTERA Stratix II FPGA

FPGA DESIGN FOR H.264/AVC ENCODER

International audienceIn this paper, we describe an FPGA H.264/AVC encoder architecture performing at real-time. To reduce the critical path length and to increase throughput, the encoder uses a parallel and pipeline architecture and all modules have been optimized with respect the area cost. Our design is described in VHDL and synthesized to Altera Stratix III FPGA. The throughput of the FPGA architecture reaches a processing rate higher than 177 million of pixels per second at 130 MHz, permitting its use in H.264/AVC standard directed to HDTV

An optimized and unified architecture design for H.265/HEVC 1-D inverse core transform

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An efficient and unified 2D-inverse integer cosine transform (IICT) FPGA-hardware implementation for HEVC standard

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Impact of varying processor number for H264 in FPGA platform

International audienceMultiprocessor architecture can be a solution to meet the increasing computational requirements for multimedia treatment algorithms such as video encoding. In this paper we study the effect of varying the processors number on resource utilization and system performance. We used Altera's NIOS II processors interconnected through Avalon bus. We vary the processors number from one to four and note its effect on the use of logic elements, DSP blocks and memory bits. We also note the change of the time execution of the Intra 16×16 chain of the H264/AVC encoder

Hardware implementation and validation of the fast variable block size motion estimation architecture for H.264/AVC

International audienceBlock matching motion estimation is the heart of video coding system. It leads to a high compression ratio, whereas it is time consuming and calculation intensive. Many fast search block matching motion estimation algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. In this paper, we propose an efficient hardware architecture of the fast line diamond parallel search (LDPS) algorithm with variable block size motion estimation (VBSME) for H.264/AVC video coding system. The design is described in VHDL language, synthesized to Altera Stratix III FPGA and to TSMC 0.18 m standard-cells. The throughput of the hardware architecture reaches a processing rate up to 78 millions of pixels per second at 83.5 MHz frequency clock and uses only 28 kgates when mapped to standard-cells. Finally, a system on a programmable chip (SoPC) implementation and validation of the proposed design as an IP core is presented using the embedded video system

AN EFFICIENT ARCHITECTURE VLSI FOR 4×4 INTRA PREDICTION IN HEVC STANDARD

International audienceThe HEVC is a proposal of new video coding standard that will be used for a wide range of applications like ULTRA HD and 3D applications. MPEG and VCEG have established a Joint Collaborative Team on Video Coding (JCT-VC) to develop the HEVC (High Efficiency Video Coding) standard which is expected to provide a significant improvement in data transmission and streaming efficiency compared to H.264. In this proposal standard, various modules of coding are defined. Among the most complex is the module of the intra prediction. The HEVC defines 35 modes of intra prediction for 8 × 8, 16 × 16, 32 × 32, 3 modes for 64 × 64 and 17 modes for 4 × 4 while the H.264/AVC (Advanced Video Coding) uses 9 modes for intra 4 × 4 and 4 modes for intra 16 × 16. In this paper, we propose an efficient uniform architecture for all of the 4 × 4 intra directional modes. This architecture offers an important gain in case of treatment time compared to the literature. Our proposed architecture is implemented with the technology TSMC 0.18μm CMO