On-Wafer Microwave De-Embedding Techniques

Wireless communication technology has kept evolving into higher frequency regime to take advantage of wider data bandwidth and higher speed performance. Successful RF circuit design requires accurate characterization of on-chip devices. This greatly relies on robust de-embedding technique to completely remove surrounding parasitics of pad and interconnects that connect device to measurement probes. Complex interaction of fixture parasitic at high frequency has imposed extreme challenges to de-embedding particularly for lossy complementary metal oxide semiconductor (CMOS) device. A generalized network de-embedding technique that avoids any inaccurate lumped and transmission line assumptions on the pad and interconnects of the test structure is presented. The de-embedding strategy has been validated by producing negligible de-embedding error (<−50 dB) on the insertion loss of the zero-length THRU device. It demonstrates better accuracy than existing de-embedding techniques that are based on lumped pad assumption. For transistor characterization, the de-embedding reference plane could be further shifted to the metal fingers with additional Finger OPEN-SHORT structures. The resulted de-embedded RF parameters of CMOS transistor show good scalability across geometries and negligible frequency dependency of less than 3% for up to 100 GHz. The results reveal the importance of accounting for the parasitic effect of metal fingers for transistor characterization

High Voltage Energy Harvesters

Green energy helps in reducing carbon emission from fossil fuel, harvesting energy from natural resources like wind to power consumer appliances. To date, many researches have been focusing on designing circuits that harvest energy from electromagnetic signals wirelessly. While it could be designed to be efficient, the generated power however is insufficient to drive large loads. Wind energy is highly available environmentally but development of small-scale energy harvesting apparatus aiming to extract significant power from miniature brushless fan has received limited attention. The aim of this chapter is to give audience an insight of different voltage multipliers used in energy harvester and knowledge on various circuit techniques to configure voltage multipliers for use in different high voltage applications. These include AC-DC converter, AC-AC converter and variable AC-DC converter

Retrospective evaluation of whole exome and genome mutation calls in 746 cancer samples

Funder: NCI U24CA211006Abstract: The Cancer Genome Atlas (TCGA) and International Cancer Genome Consortium (ICGC) curated consensus somatic mutation calls using whole exome sequencing (WES) and whole genome sequencing (WGS), respectively. Here, as part of the ICGC/TCGA Pan-Cancer Analysis of Whole Genomes (PCAWG) Consortium, which aggregated whole genome sequencing data from 2,658 cancers across 38 tumour types, we compare WES and WGS side-by-side from 746 TCGA samples, finding that ~80% of mutations overlap in covered exonic regions. We estimate that low variant allele fraction (VAF < 15%) and clonal heterogeneity contribute up to 68% of private WGS mutations and 71% of private WES mutations. We observe that ~30% of private WGS mutations trace to mutations identified by a single variant caller in WES consensus efforts. WGS captures both ~50% more variation in exonic regions and un-observed mutations in loci with variable GC-content. Together, our analysis highlights technological divergences between two reproducible somatic variant detection efforts

De-embedding techniques for characterizing high frequency noise in nanometre CMOS devices

Aggressive scaling of CMOS devices over the past decades has enabled System-on-Chip (SoC) solution which permits full integration of digital circuits with analog and RF functions in one chip at low cost. However, the growing complexity of radio frequency integrated circuits requires accurate characterization of CMOS device for successful modelling and IC design. High frequency noise measurement system has been used extensively for on-wafer noise characterization of CMOS devices. The device test fixture which consists of bond pads and interconnects provides essential connection interface between embedded transistor and measurement probes. However, undesired parasitic effects of test fixture left un-removed after calibration can significantly affect noise measurement of transistor device. Therefore, additional data processing steps, known as noise de-embedding is required to remove the impact of test structure parasitic effects from raw noise measurement data. Complex interaction of fixture parasitic at high frequency and dominance of fixture parasitic as device scaled down have imposed extreme challenges to noise de-embedding. Nevertheless, the development of a robust noise de-embedding technique is inevitable as the NFmin of CMOS device continues to decrease along the scaling trend and approach the uncertainty limit of measurement instrument. This research aims at developing an accurate noise de-embedding technique that can effectively extract noise parameters of CMOS devices of varying geometries and sizes at GHz range frequencies. Three de-embedding methods have been proposed for the purpose mentioned. The first de-embedding method is developed based on the hybrid two-port model. It is designed to remove the parasitic effects of transistor fixture for up to metal fingers while taking into consideration of contact resistance and its asymmetrical effects. The second method addresses the distributed effects of metal interconnects and forward coupling effects concurrently. It is based on a new cascade-parallel noise de-embedding methodology, which is useful for characterization of passive CMOS device as it offers de-embedding for up to the boundary of metal interconnects. The third de-embedding technique reveals the possible extension of previous cascade de-embedding approach for up to metal fingers. All these noise de-embedding methods have been verified on 130nm CMOS devices for possible application at millimeter-wave frequencies. Specifically, both the first and the last noise de-embedding methods have been shown to be scalable and accurate up to 80 GHz despite less silicon consumption by the afore-mentioned methods. The results reveal the importance of accounting for the parasitic effect of metal fingers for transistor characterization. Meanwhile, the second noise de-embedding method has been shown to be more accurate than existing cascade de-embedding approaches. The proposed de-embedding techniques discussed are also applicable to III-V compound transistor. Future noise de-embedding study could be extended for characterization of non-linear device.Doctor of Philosophy (EEE

High frequency drain current noise modeling in MOSFETs under sub-threshold condition

A new high frequency drain current noise model was developed for MOSFETs under sub-threshold condition. A simple parameter extraction technique is proposed, which utilizes Y-parameter analysis on the RF small-signal equivalent circuit. Good agreement has been obtained between the predicted and measured results up to 20 GHz.Published versio

A new unified model for channel thermal noise of deep sub-micron RFCMOS

A new unified model for circuit simulation is presented to predict the high frequency channel thermal noise of deep sub-micron MOSFETs in strong inversion region. Based on the new channel thermal noise model, the simulated channel thermal noise spectral densities of the devices fabricated in a 0.13μm RFCMOS technology process are compared to the channel noise directly extracted from RF noise measurements.Published versio

Analytical high frequency channel thermal noise modeling in deep sub-micron MOSFETs

A simple high frequency channel thermal noise model was developed for MOSFETs in strong inversion region. Short channel effects such as channel length modulation effect and mobility degradation due to vertical field were taken into account in the current-voltage model and channel thermal noise model. It was found that the long channel Tsividis’ noise model is still valid for short channel devices by including the proposed effective mobility model and the channel length modulation effect. Good agreement has been obtained between the simulated and measured results across different frequencies, gate biases and drain biases.Published versio

Impact of velocity saturation and hot carrier effects on channel thermal noise model of deep sub-micron MOSFETs

This paper discusses the impact of the short channel effects, such as channel length modulation (CLM), velocity saturation effect (VSE) and hot carrier effect (HCE), on the channel thermal noise model of short channel MOSFETs. Based on the fundamental thermal noise theory, the channel thermal noise models are derived in four different cases considering the effect of CLM only, CLM and VSE, CLM and HCE, and the combine effect of CLM, VSE and HCE. The noise reduction due to the VSE is found to be completely cancelled out by the noise increment due to the HCE for all the operating conditions

A new millimeter-wave fixture deembedding method based on generalized cascade network model

In this letter, a universal cascade-based deembedding technique was presented for on-wafer characterization of the RF CMOS device. As compared with existing deembedding approaches, it is developed based on unique combinations of two THRU structures that enable efficient deembedding of fixture parasitics without any inaccurate lumped approximation or requirement of known standards. The proposed deembedding technique is validated on 0.13- μm CMOS devices and has been proven to be more accurate than existing lumped and cascade-based deembedding techniques. As a result, it gives deeper physical prediction on transistor gate capacitances and transconductance. Therefore, it is highly suitable to be applied for device characterization at millimeter-wave frequencies