Analysis of the Implications of Stacked Devices in Nano-Scale Technologies for Analog Applications

In this work, a methodology to assess the implications on the performance of analog circuits due to the use of stacked devices in current nano-scale technologies is presented. To evaluate the usage of stacked devices, the characteristic curves of transistors implemented with a different amount of transistors in stack are obtained and compared to those of a single device. The effects of using stacked devices are further studied with the implementation of a current mirror and the implementation of two different layout topologies, discussing their tradeoffs, advantages and drawbacks. Our methodology facilitates designers to develop a good understanding of the characteristics and limitations of a particular physical design before silicon is back for laboratory testing

A Tool for the Automatic Generation and Analysis of Regular Analog Layout Modules

This paper describes the characteristics of a new CAD tool that enables the creation of layout libraries of selected analog modules. This Analog Modules Generator (AMG) automatically creates multiple layout versions of two commonly used analog structures: the differential pair and arrays of series-connected or stacked devices, for the subsequent generation of layout libraries. Based on the number of devices and rows defined by the user for the layout implementation, the tool validates all possible implementations, which are later saved in a database with their corresponding characteristics, such as area and parasitics information. Additionally, an extraction process can be optionally executed over all the layout views saved in the database. The AMG generates several reports with all the characteristics of the implemented layouts, including area and parasitic components, facilitating further statistical processing. We describe the features and capabilities of the proposed AMG tool, and several test cases are presented. Results show that optimal layout implementations can be achieved by layout and circuit designers in a reduced amount of time

Development of a CAD Tool for the Automatic Generation of Common Analog Layout Structures and Libraries

The layout implementation of analog circuits has become a critical part of the design process of integrated circuits (IC). The physical construction of this kind of circuits using transistors with digital characteristics as the only devices available in many nanoscale fabrication technologies is one of the main challenges given the limitations in the transistor’s dimensions, which are constrained to a multiple of the technology’s minimum width and length. In addition to size limitations, analog circuits have to fulfill rigorous design specifications, such as high frequency performance, low noise, and high accuracy, which are strongly dependent on their physical implementation; hence, the optimal layout implementation of the analog circuit becomes of paramount importance in the design process of an integrated circuit. On the other hand, computer-aided design (CAD) tools for analog IC physical design are far from being mature, in contrast to those used for digital IC physical design. Some of the reasons for this are that analog design, in general, is less systematic and more heuristic in nature than digital design. Additionally, analog design often requires specialized knowledge, design skills, and years of experience; analog circuits are more sensitive to parasitic disturbances, EM crosstalk, substrate noise, supply noise, etc.; besides, the variety of schematics and diversity of devices and shapes are much more significant. For all these reasons, the optimal implementation of analog layouts requires several iterations and sometimes rework of the layout, resulting in a very long and expensive developing cycle. In this doctoral dissertation, a novel CAD tool is presented that enables the creation of different layout versions for selected analog structures. The main purpose of the proposed CAD tool is the automatic generation of multiple layout topologies for the subsequent generation of layout libraries or database of two of the most fundamental analog structures: the differential pair and the array of stacked devices. Circuit designers can use this database for the analysis, characterization, optimization, and suitable implementation of their designs. The present doctoral thesis describes several tests and studies for the structures mentioned above, illustrating the functionality and capabilities of the proposed CAD tool for the creation of multiple layout topologies in a very short time, helping designers to reduce the circuit’s design cycle.La implementación física o “layout” de circuitos analógicos es una parte crítica en el proceso de diseño de circuitos integrados (CI). El “layout” de circuitos analógicos en tecnologías de fabricación nanométricas típicamente utiliza transistores con características digitales, lo cual impone uno de los principales desafíos en el diseño de CI debido a las limitaciones en las dimensiones del transistor (restringidas a la utilización de múltiplos de los valores mínimos de longitud y ancho de dichas tecnologías). Además, los circuitos analógicos deben cumplir con especificaciones muy estrictas de diseño, tales como: operación a alta frecuencia, bajo nivel de ruido y alta precisión, las que a su vez dependen de la implementación física. De aquí que la creación apropiada del “layout” es críticamente importante en el desarrollo de CI analógicos. Por otro lado, las herramientas de diseño asistido por computadora (CAD, por sus siglas en inglés) para el diseño físico de CI analógicos están aún lejos de alcanzar un estado de madurez, en contraste con aquellas para el diseño físico de CI digitales. Esto debido a que el diseño analógico es menos sistemático y más heurístico que el diseño digital, por lo que requieren conocimientos y habilidades de diseño más especializados. Adicionalmente, los CI analógicos son más sensibles a perturbaciones, elementos parásitos, interferencia electromagnética, ruido de sustrato y otras fuentes de ruido. Además, existe una amplia diversidad de esquemas para la implementación de cada módulo analógico. Es por ello que la implementación óptima de los diseños analógicos puede requerir muchas iteraciones con la intervención del diseñador experto, e incluso de varios ciclos completos de rediseño, lo que genera ciclos de desarrollo excesivamente largos y costosos. En esta disertación doctoral se presenta una novedosa herramienta de CAD que permite la generación automática de diferentes versiones de “layout” para estructuras analógicas específicas. La herramienta propuesta permite la creación eficiente de múltiples topologías de “layout” para la posterior generación de bibliotecas de dos de las estructuras analógicas más fundamentales: el par diferencial y los dispositivos apilados. Los diseñadores pueden utilizar esta base de datos para el análisis, caracterización y optimización de sus diseños. En la tesis doctoral se presentan análisis de las estructuras mencionadas, así como pruebas que ilustran la funcionalidad y capacidades de la herramienta de CAD propuesta para la creación de dichas bibliotecas de “layout” en un periodo muy corto de tiempo, ayudando a los diseñadores a reducir el ciclo de diseño del circuito.Consejo Nacional de Ciencia y TecnologíaIntel Corporatio

Synthesis tool for automatic layout generation of analog structures

In this paper, a novel analog layout synthesis tool is presented. It is focused on two common analog building blocks: differential pairs and arrays of stacked devices. Starting from a circuit netlist and the names of the selected transistors, the tool verifies that these form a valid block and creates the corresponding layout. The user can define different layout parameters and the layout view can be generated with different levels of detail. Multiple layout views of a differential pair are generated to show its effectiveness to speed up the design process