Nanostructures, Technology, Research, and Applications

Contains reports on twenty research projects and a list of publications.Joint Services Electronics Program Grant DAAH04-95-1-0038National Science Foundation Grant ECS-94-07078Semiconductor Research CorporationU.S. Army Research Office Grant DAAH04-95-1-0564Defense Advanced Research Projects Agency/Naval Air Systems Command Contract N00019-95-K-0131National Aeronautics and Space Administration Contract NAS8-38249National Aeronautics and Space Administration Grant NAGW-2003IBM Corporation Contract 1622National Science Foundation Graduate FellowshipU.S. Navy - Office of Naval Research Grant N00014-95-1-1297U.S. Army Research Office Contract DAAH04-94-G-0377U.S. Air Force - Office of Scientific Research Grant F49620-92-J-0064U.S. Air Force - Office of Scientific Research Grant F49620-95-1-0311National Science Foundation Contract DMR 94-0034U.S. Air Force - Office of Scientific Research Contract F49620-96-0126Harvard-Smithsonian Astrophysical Observatory Contract SV630304National Aeronautics and Space Administration Grant NAG5-5105Los Alamos National Laboratory Contract E57800017-9

Nanostructures Technology, Research, and Applications

Contains reports on twenty-four research projects and a list of publications.Joint Services Electronics Program Grant DAAHO4-95-1-0038Defense Advanced Research Projects Agency/Semiconductor Research Corporation SA1645-25508PGU.S. Army Research Office Grant DAAHO4-95-1-0564Defense Advanced Research Projects Agency/U.S. Navy - Naval Air Systems Command Contract N00019-95-K-0131Suss Advanced Lithography P. O. 51668National Aeronautics and Space Administration Contract NAS8-38249National Aeronautics and Space Administration Grant NAGW-2003Defense Advanced Research Projects Agency/U.S. Army Research Office Grant DAAHO4-951-05643M CorporationDefense Advanced Research Projects Agency/U.S. Navy - Office of Naval Research Contract N66001-97-1-8909National Science Foundation Graduate FellowshipU.S. Army Research Office Contract DAAHO4-94-G-0377National Science Foundation Contract DMR-940034National Science Foundation Grant DMR 94-00334Defense Advanced Research Projects Agency/U.S. Air Force - Office of Scientific Research Contract F49620-96-1-0126Harvard-Smithsonian Astrophysical Observatory Contract SV630304National Aeronautics and Space Administration Grant NAG5-5105Los Alamos National Laboratory Contract E57800017-9GSouthwest Research Institute Contract 83832MIT Lincoln Laboratory Advanced Concepts ProgramMIT Lincoln Laboratory Contract BX-655

Toward the end of the metal oxide semiconductor field-effect transistor roadmap

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.Includes bibliographical references (p. 126-133).MOSFET scaling and performance has progressed rapidly in recent years, with physical gate lengths for electrostatically sound devices reaching 30 nm or below: near the prospective scaling limits for traditional bulk MOSFETs. This work investigates several key issues for this "end of roadmap" regime. Focus is on understanding the limitations to carrier velocity in MOSFET inversion layers as channel lengths are scaled well below 100 nm, and on relaxing these limits through architectural alternatives to bulk MOSFETs. It has been proposed that drain current is ultimately limited by the rate at which carriers can be thermally injected from the source into the channel. In this work it is shown that commonly used techniques for experimentally determining carrier velocity are insufficient to determine how close modem MOSFETs operate to this ballistic or "thermal limit". A new technique is proposed, and applied to two advanced industry technologies with deep-sub-100-nm channel lengths. It is shown that a IV NMOS technology with Leff < 50 nm operates at no more than -40% of the limiting thermal velocity. Furthermore, no indication is found that continued scaling is bringing us closer to the thermal velocity limit. Via simulation, the relationship between mobility and scaling is investigated for bulk silicon NMOSFETs and FDSOI (Fully-Depleted Silicon-On-Insulator) alternatives, focusing on the 50 and 25 nm Leff generations. Scaling of bulk MOSFETs well below 100 nm Leff requires heavy channel doping, leading to degraded low-field mobility. Provided that the gate workfunction is used to determined the threshold voltage, FDSOI devices do not suffer from this trade-off, by virtue of the fact that their channel can be undoped. It is shown that single-gate FDSOI is, accordingly, an attractive alternative down to 50 nm Leff. For deeper scaling, double-gate FDSOI should have approximately a 3X mobility advantage over bulk NMOS. With careful determination of channel length, inversion-layer charge, and series resistance, it is possible to study experimentally the relation between channel length and mobility in deep-sub- 100-nm MOSFETs. With the aid of inverse modeling techniques, evidence is found that in the very shortest modern MOSFETs, mobility is less then would be expected from "universal" mobility, and independent of transverse field. This may be indicative of a transition in the dominant scattering mechanism, from surface- to Coulomb- scattering. The relevance of low-field mobility to the performance of deep-sub-100-nm MOSFETs is not well understood. In this work this relationship is studied experimentally: mobility (with low lateral electric field) is modified by externally applying uniaxial stress to NMOS devices, and the corresponding shift in carrier velocity (with high lateral field) is measured. The dependence of velocity on mobility is found to be significant, and is found to correspond well with the predictions of energy-balance modeling. Given their promise for scalability without mobility degradation, the design space for FDSOI MOSFETs merits detailed study. Via 2D simulation, scalability and drive current are investigated for three basic FDSOI alternatives: single-gate, and double-gate either with symmetrical workfunction mid-gap gates or asymmetrical workfunction n+p+ gates. For the single-gate device, it is shown that scaling below Leff = 35 nm may not be achievable for practical silicon film thickness, unless Ioff requirements are relaxed. For double-gate devices we have shown that hypothetical mid-gap top- and bottom- gates are superior to n+/p+ poly gates, for both scalability and drive current. Realization of the ideal double-gate device structure involves three major technical challenges: formation of gates above and below a thin single-crystalline silicon layer, achievement of fine alignment between top- and bottom-gates, and achieving low source/drain resistance for the thin silicon film. These issues are addressed in this work through demonstration of three primary technologies: wafer bonding with pre-patterned features, interferometric alignment, and selective epitaxy for raised source/drains.by Anthony Joseph Lochtefeld.Ph.D

Analysis of Losses in Open Circuit Voltage for an 18-μm Silicon Solar Cell

An 18 μm thin crystalline silicon solar cell was demonstrated, and its best open circuit voltage is 642.3 mV. However, this value is far from the cell’s theoretical upper limit in an ideal case. This paper explores the open circuit voltage losses of the thin silicon solar cell, starting from the ideal case, through first principle calculation and experiments. The open circuit voltage losses come from the introduced recombination due to the non-ideal surface passivation and contacts integration on front and rear surfaces, and edge isolation. This paper presents a roadmap of the open circuit voltage reduction from an ideal case of 767.0 mV to the best measured value of 642.3 mV

Precarious life and the ethics of care: Subjectivity in an Indian religious phenomenon

This article relates certain figures of the subject in an emergent Indian pilgrimage. On the basis of ethnographic research and 15 in-depth interviews, I show that these religious subjectivities, phenomenologically immersed in highly precarious material conditions, are radically relational. Observations on the pilgrimage (en)counter the cognitivist assumptions of a body of scholarly opinion on contemporary religious practice. The analyst\u27s attention to pilgrimage rituals and narratives traverses sociological, phenomenological, and psychoanalytic theories, and is, thereby, drawn to important questions of self, ethics, and time