Real-Time Blind Photonic Interference Cancellation for mmWave MIMO

Multiple-input multiple-output (MIMO) mmWave devices broadcast multiple spatially-separated data streams simultaneously in order to increase data transfer rates. Data transfer can, however, be compromised by interference. Conventional techniques for mitigating interference require additional space and power not generally available in handheld mobile devices. Here, we propose a photonic mmWave MIMO receiver architecture capable of interference cancellation with greatly reduced space and power needs. We demonstrate real-time photonic interference cancellation with an integrated FPGA-photonic system that executes a novel zero-calibration micro-ring resonator control algorithm. The system achieves sub-second cancellation weight determination latency with sub-Nyquist sampling. We evaluate the impact of canceller design parameters on performance, establishing that effective photonic cancellation is possible in handheld devices with less than 30 ms weight determination latency

A system-on-chip microwave photonic processor solves dynamic RF interference in real time with picosecond latency

Radio-frequency interference is a growing concern as wireless technology advances, with potentially life-threatening consequences like interference between radar altimeters and 5G cellular networks. Mobile transceivers mix signals with varying ratios over time, posing challenges for conventional digital signal processing (DSP) due to its high latency. These challenges will worsen as future wireless technologies adopt higher carrier frequencies and data rates. However, conventional DSPs, already on the brink of their clock frequency limit, are expected to offer only marginal speed advancements. This paper introduces a photonic processor to address dynamic interference through blind source separation (BSS). Our system-on-chip processor employs a fully integrated photonic signal pathway in the analogue domain, enabling rapid demixing of received mixtures and recovering the signal-of-interest in under 15 picoseconds. This reduction in latency surpasses electronic counterparts by more than three orders of magnitude. To complement the photonic processor, electronic peripherals based on field-programmable gate array (FPGA) assess the effectiveness of demixing and continuously update demixing weights at a rate of up to 305 Hz. This compact setup features precise dithering weight control, impedance-controlled circuit board and optical fibre packaging, suitable for handheld and mobile scenarios. We experimentally demonstrate the processor's ability to suppress transmission errors and maintain signal-to-noise ratios in two scenarios, radar altimeters and mobile communications. This work pioneers the real-time adaptability of integrated silicon photonics, enabling online learning and weight adjustments, and showcasing practical operational applications for photonic processing