3D sequential integration with Si CMOS stacked on 28nm industrial FDSOI with Cu-ULK iBEOL featuring RO and HDR pixel

International audienceThis work demonstrates for the first time the 3D sequential integration of CMOS over CMOS with advanced metal line levels (28nm Cu + ULK). The bottom tier consists of a 28nm FDSOI industrial wafer with 4 metal lines. A bevel contamination wrap module allows the return of the wafer to Front End Of Line (FEOL) environment required for achieving high performance top FET Si CMOS processing. Additionally the doped poly-Si ground plane introduced enables top FET dynamic back-biasing and effective DC and HF isolation with underlying metal lines. Finally, this 3DSI platform demonstrates functional top, bottom, and 3D ring oscillators as well as a pixel with single exposure flicker-free High Dynamic Range capability obtained thanks to the stacking of an additional circuit over a bottom 3T-pixe

Key low temperature processes for a silicon-based 3D sequential integration

International audienc

Key low temperature processes for a silicon-based 3D sequential integration

International audienc