Separating Control and Data Flow: Methodology and Automotive System Case Study

In this document we propose to study the control/data flow separation design methodology, using Scade and Mode-Automata, and its application in the design of an automotive system. This methodology allows to facilitate the specification of different kinds of systems and to have a better readability. It also separates the study of the different parts by using the most appropriate existing tools for each of them. To do that, we study a cruise control system with GPS which makes possible the control of a car speed depending on its position given by a GPS. This system combines both control and data processing and can be specified using our methodology. The goal of this work consists in presenting the application of our methodology on a real system and studing its advantages notably for formal verification

Introducing Control in the Gaspard2 Data-Parallel Metamodel: Synchronous Approach

In this document, we study the introduction of control in the Gaspard2 application UML metamodel by using the synchronous reactive system principles. This allows to take the change of running mode into account in the case of data parallel applications, and to study more general ways of mixing control and data parallel processing. Our study is applied to a particular context using two different models, exclusively dedicated to the process of computation or control. The computation part represents the Gaspard2 application metamodels based on the Array-OL language. This Language is often used to specify the data dependencies and the potential parallelism in intensive signal processing applications manipulating multidimensional data. The control part is represented by an automaton structure based on the Mode-Automata concept which makes it possible to clearly identify the different modes of a task and the switching conditions between modes. For this kind of applications, mixing control and data parallel processing, we propose an UML metamodel allowing to better visualize and control the construction of the system by clarifying, at a height abstraction level, the various relations and the possible interactions of this system. The proposed UML metamodel makes it possible to describe and to model the control automata, the different running modes and the link between control and computation parts. It also allows to clearly separate control and data parts by respecting the concurrency, the parallelism, the determinism and the compositionality of the Gaspard2 models

FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar

The ModEasy project seeks to develop techniques and software tools to aid in the development of reliable microprocessor based electronic (embedded) systems using advanced development and verification systems. The tools are to be evaluated in practical domains such as the automotive sector for reactive cruise control and anti-collision radar. We choose to define specific IPs using FPGA techniques to cover this application domain. This paper presents the implementation of such a complex and safety application on a single FPGA. The target system is composed of a reactive cruise control, a detection radar and the associated treatments

A High-level Methodology for Automatically Generating Dynamic Partially Reconfigurable Systems using IP-XACT and the UML MARTE Profile

International audienceDynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building com- plex systems remains a daunting task. Recently, approaches based on Model-Driven Engi- neering (MDE) and UML MARTE standard have emerged which aim to simplify the design of complex SoCs, and in some cases, DPR systems. Nevertheless, many of these approaches lacked a standard intermediate representation to pass from high-levels of descriptions to ex- ecutable models. However, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. We present the MARTE modeling concepts and how these models are mapped to IP-XACT objects; the emphasis is given to the generation of IP cores that can be used in the Xilinx EDK (Embedded Design Kit) environment, since we aim to develop a complete flow around their Dynamic Partial Reconfiguration design flow. Finally, we present a case study integrating the presented concepts, showing the benefits in design efforts compared with a purely VHDL approach and using solely EDK. Experimental results show a reduction of the design efforts required to obtain the netlist required for the DPR design flow from hours required in VHDL and Xilinx EDK, to less the one hour and minutes for IP integration

MEMORY REQUIREMENTS FOR HARDWARE IMPLEMENTATION OF THE H.264 ENCODER MODULES

For a hardware implementation of any image processing algorithm, it is necessary to study the input/output of each processing module  even  before  studying  the  internal  architecture  of  these modules. And  that  to  prepare  a  simulation  platform, with internal and external memory, necessary  to  load and  to prepare  the  input  for  the modules. These memories are also used as intermediate  component  between  the  different modules  to  provide  the  possibility  of  parallelism.  In  this work we  give  the architecture  of  internal  and  external  memory  used  by  the  H.264  encoder  in  order  to  develop  a  simulation  platform  for processing modules. This platform can be realized in FPGA platform chosen according to the memory requirements

Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: a XILINX EDK case study

International audienceIn this paper we present framework for the deployment of hardware IPs at high-levels of abstraction. It is based in a model- driven approach that aims at the automatic generation of Dynamic Partial Reconfiguration designs created in Xilinx Platform Studio (XPS). Contrary to previous approaches, we make use of the IP-XACT standard to facilitate the deployment of hardware IPs, their parameterization and subsequent integration. We propose an extension to the MARTE profile for IP deployment, and we introduce the necessary model transformations to obtain a high- level representation from an IP-XACT component library. These models are then used to create a platform in MARTE that abstracts the technologic aspects of the chosen back-end. The so- obtained UML platform is transformed in an IP-XACT design, which is exploited to generate the files used by XPS for system implementation. In this way, we promote IP reuse and deployment while remaining back-end independent, by using specific vendor extensions. Finally, we analyze the advantages of the proposed methodology by a case study in system integration

Une ontologie de la culture de la vigne : des savoirs académiques aux savoirs d'expérience

Dans le cadre d’un projet FUI initié en octobre 2016 (projet winecloud) visant à construire un outil de traçabilité et prédictif du cycle de la vigne et du vin, un travail sur la collecte et la nature des savoirs a été nécessaire de manière à penser un système ontologique qui se rapproche le plus du raisonnement du domaine métier. Le présent article vise plus spécifiquement à étudier le cycle de vie de la vigne. Nous rendons compte que les savoirs académiques présents dans les sources théoriques et scientifiques s’ajustent, se réactualisent à la lumière des savoirs d’expérience des viticulteurs. Ce travail s’attache également à analyser la nature protéiforme des savoirs d’expérience et à rendre compte de leur pluralité.Dans le cadre d’un projet FUI initié en octobre 2016 (projet winecloud) visant à construire un outil de traçabilité et prédictif du cycle de la vigne et du vin, un travail sur la collecte et la nature des savoirs a été nécessaire de manière à penser un système ontologique qui se rapproche le plus du raisonnement du domaine métier. Le présent article vise plus spécifiquement à étudier le cycle de vie de la vigne. Nous rendons compte que les savoirs académiques présents dans les sources théoriques et scientifiques s’ajustent, se réactualisent à la lumière des savoirs d’expérience des viticulteurs. Ce travail s’attache également à analyser la nature protéiforme des savoirs d’expérience et à rendre compte de leur pluralité

Gaspard2 UML profile documentation

This document describes the current UML profile of Gaspard2. This profile extends the UML semantics to allow the user to describe a SoC (System-on-Chip) in three steps: the application (behavior of the Soc), the hardware architecture, and the association of the application to the hardware architecture. The application is represented following a data flow model, but additional mechanisms permit the usage of control flow on those applications. In addition to those notions, the profile contains a package introducing factorization mechanisms to enable the compact description of massively parallel and repetitive systems

Enterprise Knowledge Modeling, UML vs Ontology: Formal Evaluation

International audienceEveryday activities in enterprises rely heavily on the experts' know-how. Due to experts departure, the loss of expertise and knowledge is a reoccurring problem in these enterprises. Recently, in order to capture experts knowledge into intelligent systems, formal knowledge representation methods, such as ontologies, are being studied and have caught up with non-formal or semi-formal representation, such as UML. The similarities and differences between UML class diagram and computational ontology have for long raised questions about the possibility of synthesizing them in a common representation (usually an ontology). Indeed, the problem of migrating knowledge encoded in UML into an ontology is an active research domain. This paper outlines our approach, which is based on semantic matching between existing ontologies and a UML class diagram, to support UML driven ontology refactoring and engineering

Modélisation à haut niveau du contrôle dans des applications de traitement systématique à parallélisme massif

Les travaux présentés dans cette thèse s'inscrivent dans le cadre des recherches menées sur la modélisation et la conception des systèmes sur puce à hautes performances. Ces systèmes sont basés sur des applications de traitement systématique à parallélisme massif opérant sur des données à plusieurs dimensions. Il est donc important de disposer de modèles capables de prendre en considération cet aspect multidimensionnel. Nous présentons les différents modèles de calcul existants pour la spécification de ces applications multidimensionnelles. Puis, nous nous intéressons au modèle Array-OL basé sur la seule expression des dépendances de données. Cependant, ce modèle ne prend pas en compte la modélisation des comportements de contrôle qui sont généralement indispensables dans la description de certaines applications de traitement du signal. L'objectif de notre travail est donc de proposer un modèle de spécification introduisant la notion de contrôle dans le modèle Array-OL. Nous étudions pour cela les travaux réalisés autour des systèmes réactifs synchrones, et en particulier ceux permettant la description des systèmes hybrides. Cette étude nous a permis de définir une méthodologie de conception séparant clairement le contrôle et les calculs. Nous discutons les avantages de cette méthodologie, notamment en terme de vérification formelle, et nous illustrons son application dans la conception d'un système automobile. Par la suite, nous proposons une approche basée sur un concept de degré de granularité pour associer la description du contrôle aux modèles Array-OL. Nous étudions également la possibilité d'étendre ce concept à celui de multi-degrés de granularité pour permettre la modélisation d'applications plus complexes contenant différentes parties de contrôle. Enfin, notre démarche est basée sur une approche lDM et contribue à la définition d'un profil UML pour l'environnement de développement Gaspard2. Dans ce cadre, nous détaillons la description du profil et nous illustrons son utilisation pour concevoir une application de traitement de vidéo.LILLE1-BU (590092102) / SudocSudocFranceF