Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels

Adaptive body bias (ABB) and adaptive supply voltage (ASV) have been showed to be effective methods for post-silicon tuning of circuit properties to reduce variability. While their properties have been compared on generic combinational circuits or microprocessor circuit sub-blocks, the advent of multi-core systems is bringing a new application domain forefront. Global interconnects are evolving to complex communication channels with drivers and receivers, in an attempt to mitigate the effects of reverse scaling and reduce power. The characterization of the performance spread of these links and the exploration of effective and power-aware compensation techniques for them is becoming a key design issue. This work compares the variability compensation efficiency of ABB vs ASV when put at work in two representative link architectures of today's ICs: a traditional full-swing interconnect and a low-swing signaling scheme for low-power communication. We provide guidelines for the post-silicon variability compensation of these communication channels

Tight Integration of GALS Interfaces into the NoC Architecture

This poster illustrates deep integration of of the synchronizer in the switch architecture of networks-on-chip, thus merging key tasks such as synchronization, buffering and flow control into a unique architecture block. The poster compares the integrated and the loosely coupled solutions from a performance and area viewpoint, while devoting special attention to their robustness with respect to physical design parameters

Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style

A common technique to compensate process variation induced performance deviations during post-silicon testing consists of the dynamic adaptation of processor voltage. This however comes at a significant power cost. We envision multi supply voltage design (MSV) as a promising technique to mitigate such power overhead. Voltage islands are widely recognized as the state-of-the-art in MSV design. In this paper, we develop a novel design methodology that leverages voltage islands to compensate process variations through a commercial synthesis flow. Possible violation scenarios of performance requirements in fabricated chips are pre-characterized at design time through statistical static timing analysis. Then, during post-silicon testing the supply voltage of a proper number of voltage islands is raised depending on the actual violation scenario, thus bringing performance back within nominal values. Voltage islands are generated by exploiting cell proximity for minimal perturbation of performance pre-optimized placements

Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip

We present a co-simulation environment for multiprocessor architectures, that is based on SystemC and allows a transparent integration of instruction set simulators (ISSs) within the SystemC simulation framework. The integration is based on the well-known concept of bus wrapper, that realizes the interface between the ISS and the simulator. The proposed solution uses an ISS-wrapper interface based on the standard gdb remote debugging interface, and implements two alternative schemes that differ in the amount of communication they require. The two approaches provide different degrees of tradeoff between simulation granularity and speed, and show significant speedup with respect to a micro-architectural, full SystemC simulation of the system description

Network On-Chip Design for Gigascale Systems-on-Chip

The Industrial Information Technology Handbook focuses on existing and emerging industrial applications of IT, and on evolving trends that are driven by the needs of companies and by industry-led consortia and organizations. Emphasizing fast growing areas that have major impacts on industrial automation and enterprise integration, the Handbook covers topics such as industrial communication technology, sensors, and embedded systems. The book is organized into two parts. Part 1 presents material covering new and quickly evolving aspects of IT. Part 2 introduces cutting-edge areas of industrial IT. The Handbook presents material in the form of tutorials, surveys, and technology overviews, combining fundamentals and advanced issues, with articles grouped into sections for a cohesive and comprehensive presentation. The text contains 112 contributed reports by industry experts from government, companies at the forefront of development, and some of the most renowned academic and research institutions worldwide. Several of the reports on recent developments, actual deployments, and trends cover subject matter presented to the public for the first time. Chapter 95 covers the basic principles and guidelines for network-on-chip design. First, the motivation for the design paradigm shift toward NoCs is given. Second, architecture design principles are illustrated with reference to real prototypes. Finally, the challenging issue of heterogeneous NoC design is addressed