Thermal verification on FPGAs

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. E. Boemo, and S. López-Buedo, "Thermal verification on FPGAs", 23rd in NORCHIP Conference, 2005, p. 48 - 53Thermal verification of complex ICs can help the designer to detect if a particular block is working beyond specifications. A simple method is to extract the output frequencies of an array of ring-oscillators previously distributed in the die. The main advantage is that neither external transducers nor analog parts are necessary. Other possibility is to bias one of the clamping diodes usually present in the pads, and measure its junction forward voltage. In both cases, the measurement of temperature can be done in actual working conditions; that is, with the chip inside the case with its heat sink and fan.This research is supported by project number 07T/0052/2003-3 of the Consejería de Educación de la Comunidad Autónoma de Madrid, Spain

Thermal monitoring on FPGAs using ring-oscillators

The final publication is available at Springer via http://dx.doi.org/10.1007/3-540-63465-7_212Proceedings of 7th International Workshop, FPL '97 London, UK, September 1–3, 1997In this paper, a temperature-to-frequency transducer suitable for thermal monitoring on FPGAs is presented. The dependence between delay and temperature is used to produce a frequency drift on a ring-oscillator. Different sensors have been constructed and characterized using XC4000 and XC3000 chips, obtaining typical sensibilities of 50 kHz per °C. In addition, the utility of the Xilinx OSC4 cell as thermal transducer has been demonstrated. Although a complete temperature verification system requires a control unit with a frequency counter, the use of ring-oscillators presents several advantages: minimum FPGA elements are required; no analog parts exists; the additional hardware needed (multiplexers, prescaler, etc.) can be constructed using the resources of an FPGA, the thermal-related signals can be routed employing the standard interconnection network of the board, and finally, the sensors can be dynamically inserted or eliminated.This work has been supported by the CICYT of Spain under contract TIC95-0159. The authors wish to thank Javier Garrido for his valuable contribution during the setup of the experiments

Técnicas de verificación térmica para arquitecturas dinámicamente reconfigurables

Tesis doctoral inédita leída en la Universidad Autónoma de Madrid. Escuela Politécnica Superior, Departamento de Ingeniería informática. Fecha de lectura: 27-06-200

Low-power FSMs in FPGA: Encoding alternatives

The final publication is available at Springer via http://dx.doi.org/10.1007/3-540-45716-X_36Proceedings of 12th International Workshop, PATMOS 2002 Seville, Spain, September 11–13, 2002In this paper, the problem of state encoding of FPGA-based synchronous finite state machines (FSMs) for low-power is addressed. Four codification schemes have been studied: First, the usual binary encoding and the One-Hot approach suggested by the FPGA vendor; then, a code that minimizes the output logic; finally, the so-called Two-Hot code strategy. FSMs of the MCNC and PREP benchmark suites have been analyzed. Main results show that binary state encoding fit well with small machines (up to 8 states), meanwhile One-Hot is better for large FSMs (over 16 states). A power saving of up to the 57% can be achieved selecting the appropriate encoding. An areapower correlation has been observed in spite of the circuit or encoding scheme. Thus, FSMs that make use of fewer resources are good candidates to consume less power.Ministry of Science of Spain, under Contract TIC2001-2688-C03-03, has supported this work. Additional funds have been obtained from Projects 658001 and 658004 of the Fundación General de la Universidad Autónoma de Madrid

A convolve-and-MErge approach for exact computations on high-performance reconfigurable computers

This work presents an approach for accelerating arbitrary-precision arithmetic on high-performance reconfigurable computers (HPRCs). Although faster and smaller, fixed-precision arithmetic has inherent rounding and overflow problems that can cause errors in scientific or engineering applications. This recurring phenomenon is usually referred to as numerical nonrobustness. Therefore, there is an increasing interest in the paradigmof exact computation, based on arbitrary-precision arithmetic. There are a number of libraries and/or languages supporting this paradigm, for example, the GNUmultiprecision (GMP) library. However, the performance of computations is significantly reduced in comparison to that of fixed-precision arithmetic. In order to reduce this performance gap, this paper investigates the acceleration of arbitrary-precision arithmetic on HPRCs. A Convolve-And-MErge approach is proposed, that implements virtual convolution schedules derived from the formal representation of the arbitraryprecision multiplication problem. Additionally, dynamic (nonlinear) pipeline techniques are also exploited in order to achieve speedups ranging from 5x (addition) to 9x (multiplication), while keeping resource usage of the reconfigurable device low, ranging from 11% to 19%

Fast response and coherent oscillations in small-world Hodgkin-Huxley neural networks

This is an electronic version of the paper presented at the I Jornadas Técnicas de la ETS de Informática, held in Madrid on 200

An autonomous robot that learns approach-avoidance behaviors: lessons from the brain to the robot

This is an electronic version of the paper presented at the I Jornadas Técnicas de la ETS de Informática, held in Madrid on 200

Procesamiento de imagen para seguimiento de objetos basado en MicroBlaze

En este artículo se presenta la implementación en una FPGA Xilinx Spartan- 2E de un algoritmo de seguimiento de objetos, utilizando el microprocesador embebido MicroBlaze. La flexibilidad que ofrece esta alternativa ha permitido implementar el sistema empleando sólo una FPGA, memoria externa y un decodificador de vídeo, lo que permite reducir sus costes. Adicionalmente, el uso de las librerías estándar GNU permite que sea trivial prototipar los algoritmos en un PC para más tarde implementarlos en MicroBlaze.Este trabajo ha sido financiado por los proyectos 07T/0052/2003-3 de la Consejería de Educación de la Comunidad de Madrid y 161000 de la Fundación General de la U.A.M

Comparativa del uso de HLLs en FPGA, GPU y Multicore para la aceleración de una aplicación de red IP

Afrontar la creación de aplicaciones a partir de lenguajes de alto nivel (High Level Lenguajes - HLLs) tiene la incuestionable ventaja de reducir el tiempo de desarrollo. Con ello, es viable una evaluación anticipada del prototipo para conocer cuanto antes si se alcanza el rendimiento especificado como objetivo. En este trabajo se han utilizando tres tecnologías de aceleración: multicore, coprocesador gráfico y coprocesador reconfigurable, que aprovechan el procesamiento paralelo, y se ha realizado una discusión crítica de su experiencia de uso a través de abstracciones de alto nivel. Las soluciones basadas en el uso de coprocesadores no sólo han aportado un nivel de rendimiento superior a la aplicación que se deseaba acelerar, sino que con vista al sistema final en producción, estas alternativas son especialmente interesantes por dejar libres los cores de procesamiento para la realización de las operaciones de envío/recepción en la red de comunicaciones

Labo-micro: entorno de test para la verificación de microprocesadores experimentales sobre circuitos FPGA.

Versión electrónica de la ponencia presentada en V Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica, celebrado en Las Palmas de Gran Canarias en 2002En este documento se presenta un entorno de verificación que permite comprobar el funcionamiento de un microprocesador diseñado en VHDL para ser implementado en un circuito reconfigurable del tipo FPGA. Se ha desarrollado un conjunto de herramientas que permiten a) volcar el diseño en la FPGA, b) utilizar un microcontrolador externo para cargar el programa de prueba y c) observar los resultados de su ejecución a través de una memoria de doble puerto situada entre la FPGA y el microcontrolador