20 research outputs found
Spoofing prevention via RF power profiling in wireless network-on-chip
With increasing integration in SoCs, the Network-on-Chip (NoC) connecting of cores and accelerators is of paramount importance to provide low-latency and high-throughput communication. Due to limits of scaling of electrical wires, especially for long multi-mm distances on-chip, alternate technologies such as Wireless NoC (WNoC) have shown promise. Since WNoCs can provide low-latency one-hop transfers across the entire chip, there has been a recent surge in research demonstrating their performance and energy benefits. However, little to no work has studied the additional security challenges that are unique to WNoCs. In this work, we study the potential threat of spoofing attacks in WNoCs due to malicious hardware trojans. We introduce Veritas, a drop-in solution aimed at detecting and correcting such spoofing attacks. To this end, our solution exploits the static propagation environment of WNoCs to associate each node to a power profile. We demonstrate that, with small area and power overheads, Veritas works well in a variety of settings.Peer ReviewedPostprint (author's final draft
Understanding the Impact of On-chip Communication on DNN Accelerator Performance
Deep Neural Networks have flourished at an unprecedented pace in recent
years. They have achieved outstanding accuracy in fields such as computer
vision, natural language processing, medicine or economics. Specifically,
Convolutional Neural Networks (CNN) are particularly suited to object
recognition or identification tasks. This, however, comes at a high
computational cost, prompting the use of specialized GPU architectures or even
ASICs to achieve high speeds and energy efficiency. ASIC accelerators
streamline the execution of certain dataflows amenable to CNN computation that
imply the constant movement of large amounts of data, thereby turning on-chip
communication into a critical function within the accelerator. This paper
studies the communication flows within CNN inference accelerators of edge
devices, with the aim to justify current and future decisions in the design of
the on-chip networks that interconnect their processing elements. Leveraging
this analysis, we then qualitatively discuss the potential impact of
introducing the novel paradigm of wireless on-chip network in this context.Comment: ICECS201
Quantifying the latency benefits of near-edge and in-network FPGA acceleration
Transmitting data to cloud datacenters in distributed IoT applications introduces significant communication latency, but is often the only feasible solution when source nodes are computationally limited. To address latency concerns, cloudlets, in-network computing, and more capable edge nodes are all being explored as a way of moving processing capability towards the edge of the network. Hardware acceleration using Field Programmable Gate Arrays (FPGAs) is also seeing increased interest due to reduced computation latency and improved efficiency. This paper evaluates the the implications of these offloading approaches using a case study neural network based image classification application, quantifying both the computation and communication latency resulting from different platform choices. We consider communication latency including the ingestion of packets for processing on the target platform, showing that this varies significantly with the choice of platform. We demonstrate that emerging in-network accelerator approaches offer much improved and predictable performance as well as better scaling to support multiple data sources
Spoofing Prevention via RF Power Profiling in Wireless Network-on-Chip
With increased integration in SoCs, the Network-on-Chip (NoC) connecting of cores provides low-latency and high-throughput communication. Due to limits of scaling of electrical wires, especially for long multi-mm distances on-chip, Wireless NoC (WNoC) have shown promise. Since WNoCs can provide low-latency one-hop transfers across the chip, there has been a recent surge in research demonstrating their benefits. WNoCs provide unique security challenges that have yet been unexplored. We study the potential threat of spoofing attacks in WNoCs due to malicious hardware trojans, and introduce Veritas, a drop-in solution that detects and corrects such spoofing attacks. Exploiting the static propagation environment, Veritas associates a node to a power profile. We demonstrate that, with small area and power overheads, Veritas works across a variety of settings