3 research outputs found
Non-Linear Capacitance of Si SJ MOSFETs in Resonant Zero Voltage Switching Applications
The parasitic capacitances of modern Si SJ MOSFETs are characterized by their non-linearity.
At high voltages the total stored energy Eoss(VDC) in the output capacitance Coss(v) differs substantially
from the energy in an equivalent linear capacitor Coss(tr) storing the same amount of charge. That difference
requires the de nition of an additional equivalent linear capacitor Coss(er) storing the same amount of energy
at a speci c voltage. However, the parasitic capacitances of current SiC and GaN devices have a more
linear distribution of charge along the voltage. Moreover, the equivalent Coss(tr) and Coss(er) of SiC and GaN
devices are smaller than the ones of a Si device with a similar Rds;on. In this work, the impact of the nonlinear
distribution of charge in the performance and the design of resonant ZVS converters is analyzed.
A Si SJ device is compared to a SiC device of equivalent Coss(tr), and to a GaN device of equivalent Coss(er),
in single device topologies and half-bridge based topologies, in full ZVS and in partial or full hard-switching.
A prototype of 3300 W resonant LLC DCDC converter, with nominal 400 V input to 52 V output, was
designed and built to demonstrate the validity of the analysis
A Practical Approach to the Design of a Highly Efficient PSFB DC-DC Converter for Server Applications
The phase shift full bridge (PSFB) is a widely known isolated DC-DC converter topology
commonly used in medium to high power applications, and one of the best candidates for the front-end
DC-DC converter in server power supplies. Since the server power supplies consume an enormous
amount of power, the most critical issue is to achieve high efficiency. Several organizations promoting
electrical energy efficiency, like the 80 PLUS, keep introducing higher efficiency certifications with
growing requirements extending also to light loads. The design of a high efficiency PSFB converter is
a complex problem with many degrees of freedom which requires of a sufficiently accurate modeling
of the losses and of e cient design criteria. In this work a losses model of the converter is proposed as
well as design guidelines for the efficiency optimization of PSFB converter. The model and the criteria
are tested with the redesign of an existing reference PSFB converter of 1400 W for server applications,
with wide input voltage range, nominal 400 V input and 12 V output; achieving 95.85% of efficiency at
50% of the load. A new optimized prototype of PSFB was built with the same specifications, achieving
a peak efficiency of 96.68% at 50% of the load.This research was financed by Infineon Technologies AG
On the Practical Evaluation of the Switching Loss in the Secondary Side Rectifiers of LLC Converters
N.R. and D.P.M. thank Regional Government project P20_00265 and National Government Project PID2020-117344RBI00.The switching loss of the secondary side rectifiers in LLC resonant converters can have a
noticeable impact on the overall efficiency of the complete power supply and constrain the upper
limit of the optimum switching frequencies of the converter. Two are the main contributions to
the switching loss in the secondary side rectifiers: on the one hand, the reverse recovery loss (Qrr),
most noticeably while operating above the series resonant frequency; and on the other hand, the
output capacitance (Coss) hysteresis loss, not previously reported elsewhere, but present in all the
operating modes of the converter (under and above the series resonant frequency). In this paper,
a new technique is proposed for the measurement of the switching losses in the rectifiers of the
LLC and other isolated converters. Moreover, two new circuits are introduced for the isolation and
measurement of the Coss hysteresis loss, which can be applied to both high-voltage and low-voltage
semiconductor devices. Finally, the analysis is experimentally demonstrated, characterizing the
switching loss of the rectifiers in a 3 kW LLC converter (410 V input to 50 V output). Furthermore,
the Coss hysteresis loss of several high-voltage and low-voltage devices is experimentally verified in
the newly proposed measurement circuits.Regional Government project P20_00265National Government Project PID2020-117344RBI0