78 research outputs found

    Analysis of Adhesion Molecules and Basement Membrane Contributions to Synaptic Adhesion at the Drosophila Embryonic NMJ

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    Synapse formation and maintenance crucially underlie brain function in health and disease. Both processes are believed to depend on cell adhesion molecules (CAMs). Many different classes of CAMs localise to synapses, including cadherins, protocadherins, neuroligins, neurexins, integrins, and immunoglobulin adhesion proteins, and further contributions come from the extracellular matrix and its receptors. Most of these factors have been scrutinised by loss-of-function analyses in animal models. However, which adhesion factors establish the essential physical links across synaptic clefts and allow the assembly of synaptic machineries at the contact site in vivo is still unclear. To investigate these key questions, we have used the neuromuscular junction (NMJ) of Drosophila embryos as a genetically amenable model synapse. Our ultrastructural analyses of NMJs lacking different classes of CAMs revealed that loss of all neurexins, all classical cadherins or all glutamate receptors, as well as combinations between these or with a Laminin deficiency, failed to reveal structural phenotypes. These results are compatible with a view that these CAMs might have no structural role at this model synapse. However, we consider it far more likely that they operate in a redundant or well buffered context. We propose a model based on a multi-adaptor principle to explain this phenomenon. Furthermore, we report a new CAM-independent adhesion mechanism that involves the basement membranes (BM) covering neuromuscular terminals. Thus, motorneuronal terminals show strong partial detachment of the junction when BM-to-cell surface attachment is impaired by removing Laminin A, or when BMs lose their structural integrity upon loss of type IV collagens. We conclude that BMs are essential to tie embryonic motorneuronal terminals to the muscle surface, lending CAM-independent structural support to their adhesion. Therefore, future developmental studies of these synaptic junctions in Drosophila need to consider the important contribution made by BM-dependent mechanisms, in addition to CAM-dependent adhesion

    GSTE is Partitioned Model Checking

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    Verifying whether an ?-regular property is satisfied by a finite-state system is a core problem in model checking. Standard techniques build an automaton with the complementary language, compute its product with the system, and then check for emptiness. Generalized symbolic trajectory evaluation (GSTE) has been recently proposed as an alternative approach, extending the computationally efficient symbolic trajectory evaluation (STE) to general ?-regular properties. In this paper, we show that the GSTE algorithms are essentially a partitioned version of standard symbolic model-checking (SMC) algorithms, where the partitioning is driven by the property under verification. We export this technique of property-driven partitioning to SMC and show that it typically does speed up SMC algorithms

    Translating software designs for model checking

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    This paper presents a systematic consideration of the major issues involved in translation of executable design level software specification languages to directly model-checkable formal languages. These issues are considered under the framework of integrated model/property translation and include: (1) translator architecture; (2) semantics translation from a software language to a formal language; (3) property specification and translation; (4) transformations for state space reduction; (5) translator validation and evolution. Solutions to these issues are defined, described, and illustrated in the context of translating xUML, an executable design level software specification language, to S/R, the input formal language of the COSPAN model checker

    Abstraction Refinement via Inductive Learning

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    This paper concerns how to automatically create abstractions for program analysis. We show tha

    Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings

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    International audienceWe propose a novel semi-automatic methodology to formally verify clock-domain synchronization protocols in industrial-scale hardware designs. To establish the functional correctness of all clock-domain crossings (CDCs) in a system-on-chip (SoC), semi-automatic approaches require non-trivial manual deductive reasoning. In contrast, our approach produces a small sequence of easy queries to the user. The key idea is to use counterexample-guided abstraction refinement (CEGAR) as the algorithmic back-end. The user influences the course of the algorithm based on information extracted from intermediate abstract counterexamples. The workload on the user is small, both in terms of number of queries and the degree of design insight he is asked to provide. With this approach, we formally proved the correctness of every CDC in a recent SoC design from STMicroelectronics comprising over 300,000 registers and seven million gates

    An analysis of SAT-based model checking techniques in an industrial environment

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    Model checking is a formal technique for automatically verifying that a finite-state model satisfies a temporal property. In model checking, generally Binary Decision Diagrams (BDDs) are used to efficiently encode the transition relation of the finite-state model. Recently model checking algorithms based on Boolean satisfiability (SAT) procedures have been developed to complement the traditional BDD-based model checking. These algorithms can be broadly classified into three categories: (1) bounded model checking which is useful for finding failures (2) hybrid algorithms that combine SAT and BDD based methods for unbounded model checking, and (3) purely SAT-based unbounded model checking algorithms. The goal of this paper is to provide a uniform and comprehensive basis for evaluating these algorithms. The paper describes eight bounded and unbounded techniques, and analyzes the performance of these algorithms on a large and diverse set of hardware benchmarks
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