June 7th, 2017

The most important interface in a computer system is the instruction set architecture (ISA) as it connects software to hardware. So, given the prevalence of open standards for almost all other important interfaces, why is the ISA still proprietary? We argue that a free ISA is a necessary precursor to future hardware innovation, and there is no good technical reason not to have free, open ISAs just as we have free, open networking standards and free, open operating systems. The free and open RISC-V ISA began development at UC Berkeley in 2010, with the frozen base user ISA standard released in May 2014, and has since then seen rapid uptake around the globe, including the first commercial shipments. This talk will cover the technical features of the RISC-V ISA design, which has the goals of scaling from the tiniest implementations for IoT up to the largest warehouse-scale computers, with support for extensive customization. We will also describe industry-competitive open-source cores developed at UC Berkeley, all written in Chisel, a productive new open-source hardware design language. Finally, we will describe the uptake of RISC-V and the development of the RISC-V ecosystem, including the RISC-V Foundation

Distributed-Memory Breadth-First Search on Massive Graphs

This chapter studies the problem of traversing large graphs using the breadth-first search order on distributed-memory supercomputers. We consider both the traditional level-synchronous top-down algorithm as well as the recently discovered direction optimizing algorithm. We analyze the performance and scalability trade-offs in using different local data structures such as CSR and DCSC, enabling in-node multithreading, and graph decompositions such as 1D and 2D decomposition.Comment: arXiv admin note: text overlap with arXiv:1104.451

Oтсуството на глобална валута придонесе за појава на кризата и го сопира процесот на глобализација

Процесот на глобализација кој се одвиваше мошне интензивно од 90-тите години на минатиот век доживеа забавување, па и застој, во периодот на глобалната криза и , особено, во напорите за одделните национални економии да ги надминат рецесивните и стагнантните текови. Наспроти слободното движење на стоките и услугите, на капиталот и на работната сила, форсирани и од меѓународните институции (ММФ, Светска банка и СТО), по избувнувањето на глобалната криза, дојде до појави на ограничувања на веќе либерализираната трговија меѓу одделни економии, до бегство на капитал од одделни економии во домицилните, до заострување на ограничувањата за движење на работната сила. Од повеќе страни се предупредува на опасноста од јакнее на протекционизмот во меѓународните економски односи, па дури и за можни валутни војни. Веќе неколку години повеќе се говори за опасности од „деглобализација” отколку за продолжување на процесот на глобализацијата. Опседнати со решавање на сопствените економски проблеми елитите во националните економии се плашат од засилувањето на појавите на деглобализација, но превидуваат дека продолжувањето на процесот на глобализацијата не е можно без темелно реформиање на глобалните институции и политики, пред се‘, без воспоставување на глобална валута, наспроти функционирањето на неколкуте национални во функција на светски пари

RingScalar: A Complexity-Effective Out-of-Order Superscalar Microarchitecture

RingScalar is a complexity-effective microarchitecture for out-of-order superscalar processors, that reduces the area, latency, and power of all major structures in the instruction flow. The design divides an N-way superscalar into N columns connected in a unidirectional ring, where each column contains a portion of the instruction window, a bank of the register file, and an ALU. The design exploits the fact that most decoded instructions are waiting on just one operand to use only a single tag per issue window entry, and to restrict instruction wakeup and value bypass to only communicate with the neighboring column. Detailed simulations of four-issue single-threaded machines running SPECint2000 show that RingScalar has IPC only 13% lower than an idealized superscalar, while providing large reductions in area, power, and circuit latency

Korištenje fotogrametrijskog materijala u izradi 3D modela i fototeksture

Primjena blizupredmetne fotogrametrije za 3D rekonstrukciju modela na temelju fotografija snimanih kalibriranom amaterskom kamerom stvara nove mogućosti dokumentacije, prezentacije i očuvanja arheoloških artefakata te pruža drukčiji, daleko isplativiji pristup tradicionalnim rješenjima konstrukcije 3D modela. U sklopu radionice organizirane u suradnji Geodetskog i Filozofskog fakulteta Sveučilišta u Zagrebu obrađene su fotografije replike dvodijelne posude pronađene na području Mikanovca koristeći softver Agisoft Photoscan. Rezultat rekonstrukcije je detaljan fotorealističan 3D model arheološkog artefakta

Scale Control Processor Test-Chip

We are investigating vector-thread architectures which provide competitive performance and efficiency across a broad class of application domains. Vector-thread architectures unify data-level, thread-level, and instruction-level parallelism, providing new ways of parallelizing codes that are difficult to vectorize or that incur excessive synchronization costs when multithreaded. To illustrate these ideas we have developed the Scale processor, which is an example of a vector-thread architecture designed for low-power and high-performance embedded systems. The prototype includes a single-issue 32-bit RISC control processor, a vector-thread unit which supports up to 128 virtual processor threads and can execute up to 16 instructions per cycle, and a 32 KB shared primary cache.Since the Scale Vector-Thread Processor is a large and complex design (especially for an academic project), we first designed and fabricated the Scale Test Chip (STC1). STC1 includes a simplified version of the Scale control processor, 8 KB of RAM, a host interface, and a custom clock generator. STC1 helped mitigate the risk involved in fabricating the full Scale chip in several ways. First, we were able to establish and test our CAD toolflow. Our toolflow included several custom tools which had not previously been used in any tapeouts. Second, we were able to better characterize our target package and process. For example, STC1 enabled us to better correlate the static timing numbers from our CAD tools with actual silicon and also to characterize the expected rise/fall times of our external signal pins. Finally, STC1 allowed us to test our custom clock generator. We used our experiences with STC1 to help us implement the Scale vector-thread processor. Scale was taped out on October 15, 2006 and it is currently being fabricated through MOSIS. This report discusses the fabrication of STC1 and presents power and performance results