Realization of Fractance Device using Continued Fraction Expansion Method

The realization of fractional-order circuits is an emerging area of research for people working in the areas of control systems, signal processing and other related fields. In this paper, an attempt is made to realize fractance devices. The continued fraction expansion formula is used to calculate the fractance device's rational approximation. For the simulation in the experimentation, the third-order approximation for fractional order, α = -1/2, -1/3, -1/4 is used. For the aim of mathematical simulation, the MATLAB platform was used. The proposed rational approximation is used to create a circuit. The TINA programme is used to simulate circuits. It has been discovered that the simulation and theoretical conclusions are in agreement

Artifact Removal Methods in EEG Recordings: A Review

To obtain the correct analysis of electroencephalogram (EEG) signals, non-physiological and physiological artifacts should be removed from EEG signals. This study aims to give an overview on the existing methodology for removing physiological artifacts, e.g., ocular, cardiac, and muscle artifacts. The datasets, simulation platforms, and performance measures of artifact removal methods in previous related research are summarized. The advantages and disadvantages of each technique are discussed, including regression method, filtering method, blind source separation (BSS), wavelet transform (WT), empirical mode decomposition (EMD), singular spectrum analysis (SSA), and independent vector analysis (IVA). Also, the applications of hybrid approaches are presented, including discrete wavelet transform - adaptive filtering method (DWT-AFM), DWT-BSS, EMD-BSS, singular spectrum analysis - adaptive noise canceler (SSA-ANC), SSA-BSS, and EMD-IVA. Finally, a comparative analysis for these existing methods is provided based on their performance and merits. The result shows that hybrid methods can remove the artifacts more effectively than individual methods

Design of a Fractional Order Low-pass Filter Using a Differential Voltage Current Conveyor, Journal of Telecommunications and Information Technology, 2023, nr 2

In this paper, an active implementation of a differential voltage current conveyor (DVCC) based on a low-pass filter operating in the fractional order domain is presented. The transfer function for a fractional order system is dependent on the rational approximation of sα. Different methods used for calculating the rational approximation, including Carlson, Elkhazalil, and curve fitting, are evaluated here. Finally, to validate the theoretical results, a fractional order Butterworth filter is simulated in the Pspice environment using the 0.5 micrometer CMOS technology with an R-C network-based fractional order capacitor. Additionally, using the Monte Carlo analysis, the impact of current and voltage faults on DVCC response is investigated. It has been inferred that realization with a wider bandwidth is possible