A spill code minimization algorithm for loops

Loops are the main source of parallelism in applications. The issue of finding an optimal register allocation to loops has been an open issue for some time. In this case optimal refers to the minimization of spills from registers to memory. In this paper we address this issue and present an optimal, but exponential algorithm which allocates registers to loop bodies such that the spill code is minimal. We also show heuristic modifications to the algorithm which perform in practice as well as the exponential approach. Finally, we examine this algorithm's feasibility in production compilers

Significant Effects of Antiretroviral Therapy on Global Gene Expression in Brain Tissues of Patients with HIV-1-Associated Neurocognitive Disorders

Antiretroviral therapy (ART) has reduced morbidity and mortality in HIV-1 infection; however HIV-1-associated neurocognitive disorders (HAND) persist despite treatment. The reasons for the limited efficacy of ART in the brain are unknown. Here we used functional genomics to determine ART effectiveness in the brain and to identify molecular signatures of HAND under ART. We performed genome-wide microarray analysis using Affymetrix U133 Plus 2.0 Arrays, real-time PCR, and immunohistochemistry in brain tissues from seven treated and eight untreated HAND patients and six uninfected controls. We also determined brain virus burdens by real-time PCR. Treated and untreated HAND brains had distinct gene expression profiles with ART transcriptomes clustering with HIV-1-negative controls. The molecular disease profile of untreated HAND showed dysregulated expression of 1470 genes at p<0.05, with activation of antiviral and immune responses and suppression of synaptic transmission and neurogenesis. The overall brain transcriptome changes in these patients were independent of histological manifestation of HIV-1 encephalitis and brain virus burdens. Depending on treatment compliance, brain transcriptomes from patients on ART had 83% to 93% fewer dysregulated genes and significantly lower dysregulation of biological pathways compared to untreated patients, with particular improvement indicated for nervous system functions. However a core of about 100 genes remained similarly dysregulated in both treated and untreated patient brain tissues. These genes participate in adaptive immune responses, and in interferon, cell cycle, and myelin pathways. Fluctuations of cellular gene expression in the brain correlated in Pearson's formula analysis with plasma but not brain virus burden. Our results define for the first time an aberrant genome-wide brain transcriptome of untreated HAND and they suggest that antiretroviral treatment can be broadly effective in reducing pathophysiological changes in the brain associated with HAND. Aberrantly expressed transcripts common to untreated and treated HAND may contribute to neurocognitive changes defying ART

Identification and Validation of Novel Cerebrospinal Fluid Biomarkers for Staging Early Alzheimer's Disease

Ideally, disease modifying therapies for Alzheimer disease (AD) will be applied during the 'preclinical' stage (pathology present with cognition intact) before severe neuronal damage occurs, or upon recognizing very mild cognitive impairment. Developing and judiciously administering such therapies will require biomarker panels to identify early AD pathology, classify disease stage, monitor pathological progression, and predict cognitive decline. To discover such biomarkers, we measured AD-associated changes in the cerebrospinal fluid (CSF) proteome.CSF samples from individuals with mild AD (Clinical Dementia Rating [CDR] 1) (n = 24) and cognitively normal controls (CDR 0) (n = 24) were subjected to two-dimensional difference-in-gel electrophoresis. Within 119 differentially-abundant gel features, mass spectrometry (LC-MS/MS) identified 47 proteins. For validation, eleven proteins were re-evaluated by enzyme-linked immunosorbent assays (ELISA). Six of these assays (NrCAM, YKL-40, chromogranin A, carnosinase I, transthyretin, cystatin C) distinguished CDR 1 and CDR 0 groups and were subsequently applied (with tau, p-tau181 and Aβ42 ELISAs) to a larger independent cohort (n = 292) that included individuals with very mild dementia (CDR 0.5). Receiver-operating characteristic curve analyses using stepwise logistic regression yielded optimal biomarker combinations to distinguish CDR 0 from CDR>0 (tau, YKL-40, NrCAM) and CDR 1 from CDR<1 (tau, chromogranin A, carnosinase I) with areas under the curve of 0.90 (0.85-0.94 95% confidence interval [CI]) and 0.88 (0.81-0.94 CI), respectively.Four novel CSF biomarkers for AD (NrCAM, YKL-40, chromogranin A, carnosinase I) can improve the diagnostic accuracy of Aβ42 and tau. Together, these six markers describe six clinicopathological stages from cognitive normalcy to mild dementia, including stages defined by increased risk of cognitive decline. Such a panel might improve clinical trial efficiency by guiding subject enrollment and monitoring disease progression. Further studies will be required to validate this panel and evaluate its potential for distinguishing AD from other dementing conditions

Register allocation issues in embedded code generation

In conventional compilation, register allocation—the mapping of program variables to the registers of the target architecture—plays an important role in the performance of application code. In particular, for load/store architectures, good register allocation is exceedingly important as all operands to instructions, in this type of architecture, must be contained within the register set.Typical processors selected as the core unit or core processor for an embedded system closely resemble the load/store or RISC-type of architecture, and, thus, conventional register allocation techniques are applicable in the generation of code for an embedded processor. However, architectural features of the core processor, features designed to reduce core size/cost and/or are specific to the target application area for improved performance—such as disjoint register files and/or requirements that operands to particular instructions reside in specialized registers—complicate the register allocation process. This, coupled with the time-sensitive nature of typical embedded applications necessitates high-quality register allocation.[...

A spill code minimization algorithm for loops

Loops are the main source of parallelism in applications. The issue of finding an optimal register allocation to loops has been an open issue for some time. In this case optimal refers to the minimization of spills from registers to memory. In this paper we address this issue and present an optimal, but exponential algorithm which allocates registers to loop bodies such that the spill code is minimal. We also show heuristic modifications to the algorithm which perform in practice as well as the exponential approach. Finally, we examine this algorithm's feasibility in production compilers

Optimal register allocation and assignment for loops

This paper presents a new technique for the problem of allocating and assigning registers to variables in loops. Traditionally, cyclic variables (variables written in the current iteration and read in subsequent iterations) are split at the loop boundary and treated as separate variables during register allocation and assignment. When these split variables are not assigned to the same register, register copy operations are necessary to match the register usages at the beginning and end of a loop iteration. Register copy operations, which are inherently overhead operations, have an adverse impact on the quality of the final design both in area (extra hardware—registers, busses—may be necessary) and in performance (register copy operations lengthen the schedule). Therefore, it is desirable to eliminate these spurious copy operations. In this paper, we describe a novel technique that incorporates loop unrolling into an assignment algorithm so that cyclic variables are used directly in subsequent iterations without requiring additional register copy operations, and also without requiring more registers than that used by the left-edge algorithm. We conducted experiments on some core numerical and image algorithms and observed optimal allocation

Minimization of memory traffic in high-level synthesis

In this paper we present a new transformation for the scheduling of memory accessing operations in High-Level Synthesis. This transformation is suited to memory-intensive applications with synthesized designs containing a secondary store accessed by explicit instructions. Such memory-intensive behaviors are commonly observed in video compression, image convolution, hydro-dynamics and mechatronics. Our transformation removes load instructions which become redundant during the transformation of loops. The advantage of this reduction is the decrease of secondary memory bandwidth demands. Our experiments on benchmarks from several application areas show that a significant reduction in the number of memory loads is obtainable

Ultra fine-grain percolation scheduling

Previously Percolation Based Synthesis (PBS) was proposed as a new approach to the task of scheduling in High-Level Synthesis and demonstrated favorable results. PBS is an adaptation of well-founded compiler techniques with several desirable properties (e.g. flexibility, completeness and optimality). However, the granularity of the PBS scheduler is at the functional unit level. Schedules generated at this level do not necessarily represent the best obtainable performance as they do not exploit the lower level aspects of the functional units. By scheduling at a lower level more efficient and effective schedules can be generated by utilizing the lower level information. This lower-level granularity is termed the ultra fine-grain level and the resources at this level correspond to the hardware components that are sequenced via the control unit during each clock (sub-) cycle. Therefore the schedules produced with this technique are suitable for control unit construction. The resulting impact is that it allows the ultra fine-grain code scheduler to apply parallelization techniques in the presence of low-level constraints and to utilize the underlying architecture in novel ways. In this paper we discuss the enhancement of PBS which allows the exploitation of the ultra fine-grain level. While it may seem that, due to the finer granularity, code size might increase beyond manageability, our experiments have shown that on the standard benchmark set, this was not a prohibitive factor. In fact, the increase in run-time of the code scheduler is within acceptable limits for the resultant increase in parallelism. Further, although the scheduling of this ultra fine-grain code could potentially cause simultaneous register file accesses to increase-an undesirable side-effect as building register files with a large number of ports is not currently practical-our experiments indicate that for the benchmarks studied the maximum number of simultaneous RF accesses can actually decrease

An algorithm for minimizing spill code in loops

Loops are the main source of parallelism in applications. The issue of finding an optimal register allocation to loops has been an open issue for some time. In this case optimal refers to the minimization of spills from registers to memory. In this paper we address this issue and present an optimal, but exponential algorithm which allocates registers to loop bodies such that the spill code is minimal. We also show heuristic modifications to the algorithm that performs as well as the exponential approach on typical loops from scientific code. Finally, we examine this algorithm's feasibility in production compilers