19 research outputs found

    Temperature-dependent performance of Schottky-Barrier FET ultra-low-power diode

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    In this paper, for the first time, we apply the ultra-low-power (ULP) diode concept with Schottky Barrier (SB) transistors and analyze their performance in comparison to standard CMOS, using calibrated TCAD mixed-mode simulations. The negative impedance characteristics obtained in reverse mode with SB devices are shown to offer more stable current characteristics compared to CMOS, especially as a function of temperature. The origin of this behavior manifests itself in the fact that carriers tunneling through the barrier by field emission and carriers overcoming the barrier by thermionic emission both contribute to the total device current. This enables superior current performance over temperature. This enables ultra-low-power memory application over a larger temperature range, or with a denser cell area

    Area equivalent WKB Compact modeling approach for tunneling probability in Hetero-Junction TFETs including ambipolar behaviour

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    This paper introduces an innovative modeling approach for calculating the band-to-band (B2B) tunneling probability in tunnel-field effect transistors (TFETs). The field of application is the usage in TFET compact models. Looking at a tunneling process in TFETs, carriers try to tunnel through an energy barrier which is defined by the device band diagram. The tunneling energy barrier is approximated by an approach which assumes an area equivalent (AE) triangular shaped energy profile. The simplified energy triangle is suitable to be used in the Wentzel-Kramers-Brillouin (WKB) approximation. Referring to the area instead of the electric field at individual points is shown to be a more robust approach in terms of numerical stability. The derived AE approach is implemented in an existing compact model for double-gate (DG) TFETs. In order to verify and show the numerical stability of this approach, modeling results are compared to TCAD Sentaurus simulation data for various sets of device parameters, whereby the simulations include both ON- and AMBIPOLAR-state of the TFET. In addition to the various device dimensions, the source material is also changed to demonstrate the feasibility of simulating hetero-junctions. Comparing the modeling approach with TCAD data shows a good match. Apart the limitations demonstrated and discussed in this paper, the main advantage of the AE approach is the simplicity and a better fit to TCAD data in comparison to the quasi-2D WKB approach

    2-D Physics-Based Compact DC Modeling of Double-Gate Tunnel-FETs

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    This paper presents the derivation of a compact dc modeling approach for the band-to-band tunneling current in double-gate tunnel-field effect transistors (TFETs). The physics-based model equations are solved in closed form by including 2-D effects and are implemented in the hardware description language Verilog-A. The verification of the model is done in two steps. First, the modeling approach is verified by TCAD Sentaurus simulation data of the band diagram, the transfer current, and the output current characteristics as well as the output conductance. The modeling results show a good agreement with the TCAD data. Then, measurement data of complementary nanowire gate-all-around TFET devices are utilized to verify the model and to show possible fields of application. As a part of the verification, the benefits and limitations are analyzed and discussed. The numerical stability and flexibility of the model are pointed out by performing simulations of a single-stage TFET inverter

    2-D Physics-Based Compact DC Modeling of Double-Gate Tunnel-FETs

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    Analysis and investigation of Schottky barrier MOSFET current injection with process and device simulation

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    In this paper we focus on the implementation of a process flow of SB-MOSFETs into the process simulator of the Synopsys TCAD Sentaurus tool-chain. An improved structure containing topography is briefly discussed and further device simulations are applied with the latest physical models available. Key parameters are discussed and finally the results are compared with fabricated SB-MOSFETs in terms of accuracy and capability of process simulations

    On the Physical Behavior of Cryogenic IV and III-V Schottky Barrier MOSFET Devices

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    Device Physics, Modeling and Simulation of Organic Electrochemical Transistors

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    In this work, we investigate organic electrochemical transistors (OECTs) as a novel artificial electronic device for the realization of synaptic behavior, bioelectronics, and a variety of applications. A numerical method considering the Poisson-Boltzmann statistics is introduced to reproduce associated charge densities, electrostatics and switching properties of OECTs. We shed light on the working principle of OECTs by taking into account the ionic charge distribution in the electrolyte and incomplete ionization of the organic semiconductor describing the underlying electrochemical redox reaction. This enables analyzing the OECTs electrical performance as well as a simplified chemical properties via an electrical double layer, doping and de-doping of the OMIEC layer. We have fabricated, characterized, simulated and analyzed OECTs based on PEDOT:PSS, and we show that the proposed model reveals important properties of the device’s working mechanism. The model shows a good agreement with the experimental data of the fabricated devices

    Static noise margin analysis of 8T TFET SRAM cells using a 2D compact model adapted to measurement data of fabricated TFET devices

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    In this paper a static noise margin (SNM) analysis is done for an 8T SRAM cell build up with complementary tunnel-FETs (TFETs). The simulations are done with the help of a Verilog-A implemented 2D DC compact model for a double-gate (DG) TFET, published in [1]. The compact model is adapted to measurement data of fabricated nanowire (NW) GAA TFETs before analyzing the hold/read and write SNM of the 8T TFET SRAM cell. The impact of the ambipolar behavior as well as the unidirectional current of TFETs on the SRAM cell layout and simulation are taken into account and analyzed in this work. Furthermore, the impact of various supply voltages and device widths of the access transistors on the resulting SNM are investigated
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