Non linear behavior of power HBT

To understand the linear characteristics of HBT more accurately, an analytical nonlinear HBT model using Volterra Series analysis is developed. The model considers four nonlinear components: rπ, Cdiff , Cdepl, and gm. It shows that nonlinearities of rπ and Cdiff are almost completely cancelled by gm nonlinearity at all frequencies. The residual gm nonlinearity are highly degenerated by the input impedances. Therefore, rπ, Cπ and gm nonlinearities generate less IM3 than Cbc. If Cbc is linearized, Cdepl and gm are the main nonlinear sources of HBT, and Cdepl becomes very important at a high frequency. It was also found that the degeneration resistor, RE, is more effective than RB for reducing gm nonlinearity. This analysis also provides the dependency of the source second harmonic impedance on the linearity of HBT. The IM3 of HBT is significantly reduced by setting the second harmonic impedance of ZS,2ω2 = 0 and ZS,ω2-ω1 = 0

A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL

This paper proposes a new reference-spur elimination architecture for a charge-pump-based phase locked loop (PLL) using an edge interpolation technique. By utilizing a charge-distribution mechanism on the control voltage of the voltage-controlled oscillator, the proposed architecture is capable of suppressing high-order harmonics of the reference spur, as well as a fundamental spur. In implementation, the eight-stage edge interpolator achieved more than 16-dB additional spur suppression. In addition, the harmonics of the reference spur within a 104-MHz frequency offset, the location of the eighth harmonic of the reference spur, were dramatically suppressed. The prototype PLL was fully integrated in a 0.18-mu m CMOS technology, which occupies a 670 mu m x 640 mu m active chip area. Additional circuits for the edge interpolator consumes less than one-fifth of the total area and power.close4

A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor

A programmable delay locked loop (DLL) based clock generator, providing a high multiplication factor, has been developed in a 0.18-??m CMOS technology. Utilizing the proposed pulse generator, purely consisting of D flip flops (DFFs) and inverters, the clock generator provides a high multiplication factor of up to 24. It consumes only 16.2 mW when generating 2.16 GHz output signals. In addition, the proposed saturated-type unit delay cell adopted in the voltage controlled delay line (VCDL) is capable of providing a long delay while maintaining fast-switching signal edges. Thus, the DLL can lock up an input reference frequency as low as 30 MHz while maintaining good phase noise performance and small chip area occupancy. The phase noise is - 88.7 and - 99.8 dBc/Hz at 10 kHz and 100 kHz offsets, respectively, from the operating frequency of 1.2 GHz, which is equivalent to a 1.7 ps RMS jitter. The active chip area takes only 0.051 mm2.close7

A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control

A fully integrated 2.4 GHz CMOS power amplifier (PA) in a standard 0.18 mu m CMOS process is presented. Using a parallel-combining transformer (PCT) and gate bias adaptation, a discrete power control of the PA is achieved for enhancing the efficiency at power back-off. With a 3.3 V power supply, the PA has a peak drain efficiency of 33% at 31 dBm peak output power. By applying discrete power control, a reduction of 650 mA in current consumption can be achieved over the low output power range while satisfying the EVM requirements of WLAN 802.11g and WiMAX 801.16e signals.ope