35 research outputs found

    An uptake and elimination kinetics approach to assess the bioavailability of chromium, copper, and arsenic to earthworms (Eisenia andrei) in contaminated field soils

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    The aim of this study was to determine the bioavailability of metals in field soils contaminated with chromated copper arsenate (CCA) mixtures. The uptake and elimination kinetics of chromium, copper, and arsenic were assessed in the earthworm Eisenia andrei exposed to soils from a gradient of CCA wood preservative contamination near Hartola, Finland. In soils contaminated with 1480–1590 mg Cr/kg dry soil, 642–791 mg Cu/kg dry soil, and 850–2810 mg Ag/kg dry soil, uptake and elimination kinetics patterns were similar for Cr and Cu. Both metals were rapidly taken up and rapidly excreted by Eisenia andrei with equilibrium reached within 1 day. The metalloid As, however, showed very slow uptake and elimination in the earthworms and body concentrations did not reach equilibrium within 21 days. Bioaccumulation factors (BAF) were low for Cu and Cr (Peer reviewe

    Toxicity of binary mixtures of Cu, Cr and As to the earthworm Eisenia andrei

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    Chromated copper arsenate (CCA) mixtures were used in the past for wood preservation, leading to large scale soil contamination. This study aimed at contributing to the risk assessment of CCA-contaminated soils by assessing the toxicity of binary mixtures of copper, chromium and arsenic to the earthwormEisenia andreiin OECD artificial soil. Mixture effects were related to reference models of Concentration Addition (CA) and Independent Action (IA) using the MIXTOX model, with effects being related to total and available (H2O and 0.01 M CaCl(2)extractable) concentrations in the soil. Since only in mixtures with arsenic dose-related mortality occurred (LC(50)92.5 mg/kg dry soil), it was not possible to analyze the mixture effects on earthworm survival with the MIXTOX model. EC(50)s for effects of Cu, Cr and As on earthworm reproduction, based on total soil concentrations, were 154, 449 and 9.1 mg/kg dry soil, respectively. Effects of mixtures were mainly antagonistic when related to the CA model but additive related to the IA model. This was the case when mixture effects were based on total and H2O-extractable concentrations; when based on CaCl2-extractable concentrations effects mainly were additive related to the CA model except for the Cr-As mixture which acted antagonistically. These results suggest that the CCA components do interact leading to a reduced toxicity when present in a mixture.Peer reviewe

    Nano-thermoelectric infrared bolometers

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    Infrared (IR) radiation detectors are used in numerous applications from thermal imaging to spectroscopic gas sensing. Obtaining high speed and sensitivity, low-power operation and cost-effectiveness with a single technology remains to be a challenge in the field of IR sensors. By combining nano-thermoelectric transduction and nanomembrane photonic absorbers, we demonstrate uncooled IR bolometer technology that is material-compatible with large-scale CMOS fabrication and provides fast and high sensitivity response to long-wavelength IR (LWIR) around 10 ÎĽ\mum. The fast operation speed stems from the low heat capacity metal layer grid absorber connecting the sub-100 nm-thick n- and p-type Si nano-thermoelectric support beams, which convert the radiation induced temperature rise into voltage. The nano-thermoelectric transducer-support approach benefits from enhanced phonon surface scattering in the beams leading to reduction in thermal conductivity, which enhances the sensitivity. We demonstrate different size nano-thermoelectric bolometric photodetector pixels with LWIR responsitivities, specific detectivities and time constants in the ranges 179-2930 V/W, 0.15-3.1â‹…108\cdot10^{8} cmHz1/2^{1/2}/W and 66-3600 ÎĽ\mus, respectively. We benchmark the technology against different LWIR detector solutions and show how nano-thermoelectric detector technology can reach the fundamental sensitivity limits posed by phonon and photon thermal fluctuation noise.Comment: 20 pages, 4 figures, 1 tabl

    Galliumarsenidinanolankojen planarisointi

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    In this work gallium arsenide nanowire ensembles were planarized and contacted. These group III-V semiconductor nanowires possess many interesting properties for optoelectronic and electronic devices. However, their reliable integration to functional devices remains one of the major challenges. Vertical integration of the nanowires can be done by fabricating an insulation layer between the top of the nanowires and the substrate before deposition of metal contacts. The aim of this work was to find optimal filling materials for the planarization of different kinds of nanowire structures. Nanowire samples with different diameter and length were used. The aim was to find a material, which creates a void and crack free insulation layer without destroying the nanowires. H-PDMS, parylene and three different polymers, SOG 111, SOG B512 and Accuflo from Honeywell, were used. Structures were characterized by scanning electron microscope, current-voltage and optical measurements. The results showed that B512 and Accuflo were good insulation layers, while other filling materials possessed cracks and voids. In addition, Accuflo destroyed several nanowires, thus only B512 was observed to be a reliable planarization material. Insulation of B512 was confirmed by current-voltage measurements.Tässä työssä planarisoitiin ja kontaktoitiin galliumarsenidinanolankarakenteita. Näillä III-V -ryhmien puolijohteilla on monia optoelektroniikan ja elektroniikan sovellusten kannalta kiinnostavia ominaisuuksia. Nanolankarakenteiden yksi ongelmista on niiden kontaktointi luotettavasti. Pystysuorien nanolankarakenteiden kontaktoiminen vaatii eristävän ohutkalvon kasvattamista nanolankojen ja substraatin väliin. Tätä menetelmää kutsutaan planarisoinniksi. Työn tarkoituksena oli löytää sopivia materiaaleja erilaisten nanolankarakenteiden planarisointiin. Tarkoituksena oli löytää materiaali, joka muodostaisi reiättömän ja halkeilemattoman ohutkalvon ilman että nanolankoja vahingoitetaan valmistuksen aikana. Työssä planarisointiin käytettiin H-PDMS, paryleeni, SOG 111, SOG B512 ja Accuflo polymeerejä. Rakenteita tutkittiin elektronipyyhkäisymikroskoopilla sekä optisilla ja virtajännitemittauksilla. Huomattiin, että SOG B512 ja Accuflo muodostivat reiättömän ohutkalvon lankojen väliin, kun taas muissa polymeereissä havaittiin aukkoja ja halkeamia. Accuflo kuitenkin tuhosi useita nanolankoja, joten B512:n todettiin olevan luotettavin materi-aali ja sen eristävyys varmennettiin virtajännitemittauksilla

    Vertical III-V Nanowire MOSFETs

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    Vertical III-V nanowire MOSFETs are interesting candidates for future digital and analog applications. High electron velocity III-V materials allow fabrication of low power and high frequency MOSFETs. Vertical vapor-liquid-solid growth enables fabrication of axial and radial heterostructure nanowires. This enables fabrication of novel structures where the band-gap can be engineered in the electron transport direction.In this thesis, vertical InAs/InGaAs DC and RF MOSFETs on Si are fabricated and characterized. Several novel structures in vertical nanowire MOSFETs have been implemented such as gate-last process, axial/radial heterostructures, sub-30-nm gate-length, optimized RF design and field-plate structures. Several different nanowire compositions, such as InAs, InAs/In0.7Ga0.3As and InAs/In0.4Ga0.6As, were used. The radial heterostructureand the gate-last process enabled a record low access resistance in these devices. The axial heterostructure, on the other hand, allowed a wider band-gap material on the drain side, therefore suppressing the band-to-band tunnelling and impact ionization. This enabled a considerable improvement in the transistor off-state performance and for the first time Ioff 100 GHz / 100 GHz

    Sub-100-nm gate-length scaling of vertical InAs/InGaAs nanowire MOSFETs on Si

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    We demonstrate a process to vary the gate-length of vertical MOSFETs on the same sample with high accuracy and high performance. Fabricated vertical InAs/InGaAs MOSFETs on Si have gate length ranging from 25 nm to 140 nm. The results shown are from single nanowire transistors as well as arrays with nanowires ranging from 80 to 500 nanowires. The devices show good yield and clear scaling trends. We demonstrate a device with gm = 2.4 mS/ÎĽm and a device with Ion = 407 ÎĽA/ÎĽm at Ioff = 100 nA/ÎĽm and VDD = 0.5 V, which both are record values for vertical MOSFETs. This is the first demonstration of vertical MOSFETs having gatelengths comparable to the state-of-the-art lateral III-V MOSFETs

    Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs

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    Vertical InAs/InGaAs nanowire MOSFETs are fabricated in a gate-last fabrication process, which allows gate-lengths down to 25 nm and accurate gate-alignment. These devices demonstrate high performance with transconductance of 2.4 mS/μm, high on-current, and off-current below 1 nA/μm. An in-depth analysis of the heterostructure MOSFETs are obtained by systematically varying the gate-length and gate location. Further analysis is done by using virtual source modeling. The injection velocities and transistor metrics are correlated with a quasi-ballistic 1-D MOSFET model. Based on our analysis, the observed performance improvements are related to the optimized gate-length, high injection velocity due to asymmetric scattering, and low access resistance

    Effects of traps in the gate stack on the small-signal RF response of III-V nanowire MOSFETs

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    We present a detailed study of the effect of gate-oxide-related defects (traps) on the small-signal radio frequency (RF) response of III-V nanowire MOSFETs and find that the effects are clearly identifiable in the measured admittance parameters and in important design parameters such as h21 (forward current gain) and MSG (maximum stable gain). We include the identified effects in a small-signal model alongside results from previous investigations of III-V RF MOSFETs and thus provide a comprehensive physical small-signal RF model for this type of transistor, which accurately describes the measured admittance parameters and gains. We verify the physical basis of the model assumptions by calculating the oxide defect density from the measured admittances
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