Min/max time limits and energy penalty of communication scheduling in ring-based ONoC

International audienceRecent advances in the photonics devices integration bring ONoC as a bridge future for communication media in the MPSoC domain. As ONoC can support Wavelength Division Multiplexing (WDM) technique, communications between cores can be improved through allocation of one or several wavelengths for each communication. However, WDM introduces wavelength crosstalk, requiring to increase the laser power to provide accurate communication between cores. Thus, for the designer, exploring this design space (execution time vs power consumption) is not an easy task due to a large number of wavelength allocation combinations. The contribution presented in this paper proposes to evaluate the two extreme bounds of this design space considering the different communication scenario. To address this problem, we model the wavelength allocation by two different objective functions to compute the bounds in terms of execution times. Furthermore, from an accurate model of crosstalk between the wavelengths, we compute the energy penalty for each communication scenario. The results presented in this paper highlight the execution time and energy consumption tradeoff, and the opportunity for communication optimisation thanks to an efficient use of WDM technique

Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques

International audienceNanophotonic is an emerging technology considered as one of the key solutions for future generation on-chip interconnects. Indeed, this technology provides high bandwidth for data transfers and can be a very interesting alternative to bypass the bottleneck induced by classical NoC. However, their implementation in fully integrated 3D circuits remains uncertain due to the high power consumption of on-chip lasers. However, if a specific bit error rate is targeted, digital processing can be added in the electrical domain to reduce the laser power and keep the same communication reliability. This paper addresses this problem and proposes to transmit encoded data on the optical interconnect, which allows for a reduction of the laser power consumption, thus increasing nanophotonics interconnects energy efficiency. The results presented in this paper show that using simple Hamming coder and decoder permits to reduce the laser power by nearly 50% without loss in communication data rate and with a negligible hardware overhead

Optimization of a Reliable Network on Chip dedicated to partial reconfiguration

International Conference on Control, Decision and Information Technologies (CoDIT), Ecole Natl Ingenieurs Metz, Metz, FRANCE, NOV 03-05, 2014International audienceWe present an optimization of reliable Network on Chip (NoC) structure dedicated to dynamic reconfigurable systems (DRS) based on FPGA. The originality of our approach is based on a strategic placement of router incorporating elements of dependability. The solution is a factorization of these reliable routers encompassing routers without any error detection block. This ensures the global reliability of the network and reduce the cost of area, the latency of the data packets and the power consumption. The proposed approach can be applied to the majority NoC topologies

Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window

International audienceError detection and correction based on double-sampling is used as common technique to handle timing errors while scaling V dd for energy efficiency. An additional sampling element is inserted in the critical paths of the design, to double sample the outputs of those logic paths at different time instances that may fail while scaling the supply voltage or the clock frequency of the design. However, overclocking, and error detection and correction capabilities of the double sampling methods are limited due to the fixed speculation window which lacks adaptability for tracking variations such as temperature. In this paper, we introduce a dynamic speculation window to be used in double sampling schemes for timing error detection and correction in pipelined logic paths. The proposed method employs online slack measurement and conventional shadow flipflop approach to adaptively overclock or underclock the design and also to detect and correct timing errors due to temperature and other variability effects. We demonstrate this method in the Xilinx Virtex VC707 FPGA for various benchmarks. We achieve a maximum of 71% overclocking with a limited area overhead of 1.9% LUTs and 1.7% flip-flops

Robust Image Encryption based on a Synchronized Hybrid Discrete Continuous Chaotic System

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Pushing the Limits of Voltage Over-Scaling for Error-Resilient Applications

International audienceVoltage scaling has been used as a prominent technique to improve energy efficiency in digital systems, scaling down supply voltage effects in quadratic reduction in energy consumption of the system. Reducing supply voltage induces timing errors in the system that are corrected through additional error detection and correction circuits. In this paper we are proposing voltage over-scaling based approximate operators for applications that can tolerate errors. We characterize the basic arithmetic operators using different operating triads (combination of supply voltage, body-biasing scheme and clock frequency) to generate models for approximate operators. Error-resilient applications can be mapped with the generated approximate operator models to achieve optimum trade-off between energy efficiency and error margin. Based on the dynamic speculation technique, best possible operating triad is chosen at runtime based on the user definable error tolerance margin of the application. In our experiments in 28nm FDSOI, we achieve maximum energy efficiency of 89% for basic operators like 8-bit and 16-bit adders at the cost of 20% Bit Error Rate (ratio of faulty bits over total bits) by operating them in near-threshold regime

BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation

International audienceSince several decades, fault tolerance has become a major research field due to transistor shrinking and core number increasing in System-on-Chip (SoC). Especially, faults occurring to Network-on-Chips (NoCs) of those systems have a significant impact, due to the high amount of data, crossing the NoC, for the communication among Intellectual Properties (IPs). Furthermore, existing fault tolerant approaches cannot efficiently deal with several permanent faults, which occur in NoC routers. To address these limitations, we propose the Bit Shuffling meThod (BiSuT) for fault tolerant NoCs that reduces the impact of faults on data communications. To achieve that, the proposed approach exploits, at run-time, the position of permanent faults and changes the order of bits inside a flit. Our method reduces, as much as possible, the impact of faults by transferring the faults on Least Significant Bits (LSBs), instead of keeping them on Most Significant Bits (MSBs). The results obtained by extensive evaluations show that BiSuT can reduce the impact of multiple permanent faults, with low hardware costs, compared to existing approaches, like Hamming code

Interface Electrique/Optique pour un ONoC

National audienceOptical Network-on-Chips are nowadays a mature technology which can be embedded in high performance multi-processors to support high bandwidth communications. This technology enables the use of several wavelengths for the same communication to increase the bandwidth and decrease the communication time. Nevertheless, supporting such high bandwidth need efficient interface between electrical and optical domains. This paper presents the interface developed to manage the wavelength allocation, but also to support the management of laser power in order to reduce the power consumption. This power consumption reduction by exploiting the tradeoff between data encoding in electrical domain and energy needed in optical domain to produce wavelengths through lasers.La photonique sur silicium a fait d'énormes progrès depuis quelques années, permettant d'intégrer des composants optiques au sein d'architectures multi-couches. Dans ce contexte, il est donc maintenant possible de proposer l'intégration de NoC optique (ONoC) au sein d'une architecture multiprocesseurs afin de supporter deséchangesdeséchanges extrêmement efficaces entre les coeurs de calcul. Une communication dans un ONoC s'effectue alors via des lasers, utilisable enparalì ele sur des longueurs d'ondes distinctes, permettant la transmission d'information sériè a 10Gbit/s sur chacune d'elles. Toutefois, pour bénéficier de ces débits, lesélémentsleséléments clés de l'association d'un ONoC au sein d'une architecturé electrique sont les interfacesélectriqueinterfacesélectrique ↔ optique qui doivent pouvoir supporter des fréquences de conversionparalì ele/sérié elevées. Cet article se situe dans ce contexte et propose une interface pour la gestion d'un NoC optique pour deséchangesdeséchanges entre des tâches réparties sur différents coeurs d'une architecture multi-coeurs. L'interface proposée permet de supporter l'allocation de longueurs d'ondes et permetégalementpermetégalement une gestion de la consommationénergétiqueconsommationénergétique via l'utilisation de codes correcteurs d'erreurs afin de réduire la puissance d'´ emission des lasers. Cet article illustre le fonctionnement de cette interface et donne les résultats d'implémentation de celle-ci pour une technologie FDSOI 28nm

Intégration d'un NoC optique au sein d'une architecture multi-coeurs

International audienceL'intégration de NoC optique au sein d'une architecture multi-coeurs est une opportunité intéressante pour supporter les communications entre les éléments de calcul. Toutefois, pour être pleinement utilisable, il est nécessaire de définir une interface électrique / optique pour supporter les fonctions de base des communications. Nos travaux se situent dans ce contexte et nous exposons ici l'interface développée pour l'intégration d'un NoC optique dans une architecture multi-coeurs. L'inter-face proposée supporte trois fonctionnalités de base qui sont : i) l'encodage des données avec codes correcteur d'erreurs, ii) la gestion de la consommation énergétique des lasers, et iii) l'allocation de longueurs d'ondes

Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques

International audienceNanophotonic is an emerging technology considered as one of the key solutions for future generation on-chip interconnects. Indeed, this technology provides high bandwidth for data transfers and can be a very interesting alternative to bypass the bottleneck induced by classical NoC. However, their implementation in fully integrated 3D circuits remains uncertain due to the high power consumption of on-chip lasers. However, if a specific bit error rate is targeted, digital processing can be added in the electrical domain to reduce the laser power and keep the same communication reliability. This paper addresses this problem and proposes to transmit encoded data on the optical interconnect, which allows for a reduction of the laser power consumption, thus increasing nanophotonics interconnects energy efficiency. The results presented in this paper show that using simple Hamming coder and decoder permits to reduce the laser power by nearly 50% without loss in communication data rate and with a negligible hardware overhead