Stochastic Analysis of LMS Algorithm with Delayed Block Coefficient Adaptation

In high sample-rate applications of the least-mean-square (LMS) adaptive filtering algorithm, pipelining or/and block processing is required. In this paper, a stochastic analysis of the delayed block LMS algorithm is presented. As opposed to earlier work, pipelining and block processing are jointly considered and extensively examined. Different analyses for the steady and transient states to estimate the step-size bound, adaptation accuracy and adaptation speed based on the recursive relation of delayed block excess mean square error (MSE) are presented. The effect of different amounts of pipelining delays and block sizes on the adaptation accuracy and speed of the adaptive filter with different filter taps and speed-ups are studied. It is concluded that for a constant speed-up, a large delay and small block size lead to a slower convergence rate compared to a small delay and large block size with almost the same steady-state MSE. Monte Carlo simulations indicate a fairly good agreement with the proposed estimates for Gaussian inputs.Comment: 13 pages, 8 figure

Coat Protein Gene based Characterization of Cucumber Mosaic Virus Isolates Infecting Banana in India

Banana plants showing typical yellow stripes on leaves as symptoms, in addition to leaf distortion and stunting of plant were collected from Karnataka (KAR), Maharashtra (MH) and Uttar Pradesh (UP) in India. The causal agent was identified as Cucumber mosaic virus (CMV) on the basis of transmission electron microscopy and reverse transcription polymerase chain reaction (RT-PCR). Complete coat protein (CP) gene of all isolates were amplified using gene specific primers for coat protein (CP), followed by cloning into desired cloning vector for sequencing. Sequenced region were found containing complete single open reading frame of 657 nucleotides, potentially coding 219 amino acids. Sequence analysis of CP gene showed 93%-98% (at nucleotide) and 94%-99% (at amino acid) sequence identity between all three Indian isolates. On comparing CP gene sequences of CMV KAR, CMV MH and CMV UP with CMV P isolate (Physalis minima); we got 94%, 99% and 96% identity respectively. High degree identity at nucleotide level between these isolates of banana and Physalis minima (a weed) suggest that Physalis minima could be an alternate host of CMV banana. Phylogenetic analysis of nucleotide along with amino acid sequence of coat protein gene revealed that all our isolates belong to IB subgroup.  In short, it appears that there occurs a high incidence of CMV infecting banana belonging to IB subgroup in most parts of Indian subcontinent.Key words: Banana, CMV, CP gene, RT-PC

Analyzing Step-Size Approximation for Fixed-Point Implementation of LMS and BLMS Algorithms

In this work, we analyze the step-size approximation for fixed-point least-mean-square (LMS) and block LMS (BLMS) algorithms. Our primary focus is on investigating how step size approximation impacts the convergence rate and steady-state mean square error (MSE) across varying block sizes and filter lengths. We consider three different FP quantized LMS and BLMS algorithms. The results demonstrate that the algorithm with two quantizers in single precision behaves approximately the same as one quantizer under quantized weights, regardless of block size and filter lengths. Subsequently, we explore the approximation effects of nearest power-of-two and their combinations with different design parameters on the convergence performance. Simulation results for within the context of a system identification problem under these approximations reveal intriguing insights. For instance, a single quantizer algorithm without quantized error is more robust than its counterpart under these approximations. Additionally, both single quantizer algorithms with combined power-of-two approximations matches the behavior of the actual step-size.</p

An Area and Energy Efficient Serial-Multiplier

In this work, we present an area and energy-efficient serial multiplier. Specifically, we exploit symmetries in odd and even partial products (PPs) in its radix-γ implementation. Subsequently, we express them as ∓ (2k±1) with 1≤k≤log2γ−1, which enable to reduce the hardware resources. For γ≥16, the above representation becomes invalid, requiring additional power-of-two terms and raising hardware costs. To address this, we utilize recursive symmetries in PPs, which enable time-sharing and reduce the logic resources for efficient realization. ASIC synthesis results show the proposed design has substantial savings in area and energy than the state-of-the-art design

ASIC Implementation Trade-Offs for High-Speed LMS and Block LMS Adaptive Filters

In this work, implementation trade-offs for ASIC-implementation of least-mean-square (LMS) and block LMS (BLMS) adaptive filters are presented. We explore the design trade-offs by increasing the block size and/or relying on the synthesis tool for increased sample rate. For area, lower block size is advantageous as long as the synthesis tool can meet timing. Energy optimum is however found at a different point in design space. Simulation confirms that longer block sizes leads to lower MSE errors for identical step-size. Hence, the design-point should be decided based on weighted requirements for area, energy and MSE

Stochastic Analysis of LMS Algorithm with Delayed Block Coefficient Adaptation

In high sample-rate applications of the least-mean-square (LMS) adaptive filtering algorithm, pipelining or/and block processing is required. As opposed to earlier work, pipelining and block processing are jointly considered to obtain what we refer to as the delayed block LMS (DBLMS) algorithm. Different stochastic analyses for the steady and transient states to estimate the step-size bound, adaptation accuracy, and adaptation speed based on the recursive relation of delayed block excess mean square error (MSE) are presented. The effect of different amounts of pipelining delays and block sizes on the adaptation accuracy and speed of the adaptive filter with different filter lengths and speed-ups are studied. It is concluded that for a constant speed-up, a large delay and small block size lead to a slower convergence rate compared to a small delay and large block size with almost the same steady-state MSE. Monte Carlo simulations indicate a good agreement with the proposed estimates for Gaussian inputs

An Area and Energy Efficient Serial-Multiplier

In this work, we present an area and energy-efficient serial multiplier. Specifically, we exploit symmetries in odd and even partial products (PPs) in its radix-γ implementation. Subsequently, we express them as ∓ (2k±1) with 1≤k≤log2γ−1, which enable to reduce the hardware resources. For γ≥16, the above representation becomes invalid, requiring additional power-of-two terms and raising hardware costs. To address this, we utilize recursive symmetries in PPs, which enable time-sharing and reduce the logic resources for efficient realization. ASIC synthesis results show the proposed design has substantial savings in area and energy than the state-of-the-art design

High-Performance VLSI Architecture of DLMS Adaptive Filter for Fast-Convergence and Low-MSE

This brief presents a high-performance VLSI architecture of delayed least mean square (DLMS) adaptive filter for fast-convergence and low-mean square error (MSE) using distributed arithmetic (DA). The proposed design estimates response against the adaptation delays using a parallel predictive adder tree followed by a shift accumulate (SA) unit. An efficient quantization scheme with two bits of scaled error signal is also suggested. Single SA unit for multiple DA bases is used to reduce the number of adders and registers. Simulation and synthesis results show that the proposed design for 32nd order provides 19.72% lesser area, 25.51% lesser power, lesser 28.89% MSE and 59.91% lesser MSE/area over the best existing design.</p

High-Throughput and Improved-Convergent Design of Pipelined Adaptive DFE for 5G Communication

This brief presents a high-throughput and improved convergent design of pipelined adaptive decision feedback equalizer (ADFE) for 5G communication system. The proposed ADFE design achieves 3.3 Gbps for 4-quadrature amplitude modulation (4-QAM) and 8th order feedback filter (FBF). A novel look-up table update scheme for M-ary QAM ADFE is proposed. Further, we present an efficient quantization scheme for the proposed design. Theoretical derivations and simulation results confirm that the convergence performance of the proposed ADFE is superior. For instance, the proposed design for 16-QAM and 16th order FBF takes 167 less iterations and improves 4.03 dB error performance, while it provides nearly 8.96 times higher throughput as compared to the best existing design