Manganese Induces Oxidative Stress, Redox State Unbalance and Disrupts Membrane Bound ATPases on Murine Neuroblastoma Cells In Vitro: Protective Role of Silymarin

Manganese (Mn) is an essential trace element required for ubiquitous enzymatic reactions. Chronic overexposure to this metal may promote potent neurotoxic effects. The mechanism of Mn toxicity is not well established, but several studies indicate that oxidative stress play major roles in the Mn-induced neurodegenerative processes. Silymarin (SIL) has antioxidant properties and stabilizes intracellular antioxidant defense systems. The aim of this study was to evaluate the toxic effects of MnCl2 on the mouse neuroblastoma cell lines (Neuro-2A), to characterize the toxic mechanism associated with Mn exposure and to investigate whether SIL could efficiently protect against neurotoxicity induced by Mn. A significant increase in LDH release activity was observed in Neuro-2A cells associated with a significant decrease in cellular viability upon 24 h exposure to MnCl2 at concentrations of 200 and 800 μM (P < 0.05) when compared with control unexposed cells. In addition, exposure cells to MnCl2 (200 and 800 μM), increases oxidant biomarkers and alters enzymatic and non enzymatic antioxidant systems. SIL treatment significantly reduced the levels of LDH, nitric oxide, reactive oxygen species and the oxidants/antioxidants balance in Neuro-2A cells as compared to Mn-exposed cells. These results suggested that silymarin is a powerful antioxidant through a mechanism related to its antioxidant activity, able to interfere with radical-mediated cell death. SIL may be useful in diseases known to be aggravated by reactive oxygen species and in the development of novel treatments for neurodegenerative disorders such as Alzheimer or Parkinson diseases

Un nouveau type d'observateur impulsionnel

International audienceDans cet article, dans un premier temps, un nouveau type d'observateur hybride pour une classe de systèmes linéaires continus avec des mesures discrètes est présenté. L'approche utilisée est basée sur des conditions suffisantes de stabilité des systèmes dynamiques linéaires impulsifs. Celles-ci seront rappelées. Puis, des exemples seront donnés afin de mettre en évidence la conception de ces observateurs et montrer que ceux-ci sont généralisables aux systèmes non linéaires et aux mesures de type clairsemé (c-'a-d en dessous de la fréquence de Shannon-Nyquist)

A high sensitivity and low power circuit for the measurement of abnormal blood cell levels

This paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65nm CMOS technology and post-layout simulations shows 15.25aF sensitivity. The total circuit occupies 2184µm2 silicon area and consumes 216µA from a 1V power supply

Vers une personnalisation de la navigation par l'apprentissage de profils utilisateurs.

International audienceL'exploitation des interaction utilisateurs-sites Web peut jouer un rôle important pour l'amélioration de la navigation dans le futur Web. Dans une mesure plus particulière, dégager et reconnaître les profils des internautes à partir de ces données peut aider les navigateurs et les sites Web à personnaliser les sessions utilisateurs tout en recommandant des ressources spécifiques. Nous présentons à travers ce papier une solution de reconnaissance de profils basée sur les technologies du Web sémantique. Cette approche tire ses avantages de l'utilisation des ontologies, des annotations sémantiques sur les ressources Web et d'un moteur d'inférence et d'un moteur de recherche sémantique

A start-up assisted fully differential folded cascode opamp

This paper explains the hidden positive feedback in the two-stage fully differential amplifier through external feedback resistors, and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascode branches have been explained intuitively, With reference to previous literature. To avoid the latch-up problem irrespective of the transistor bias currents a novel, hysteresis based start-up circuit is proposed. An 87dB, 250MHz unity gain bandwidth amplifier has been developed in 65nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126uA from a 1.2V supply and occupies the 2184um2 area

An OTA gain enhancement technique for low power biomedical applications

The performance requirement of an operational trans-conductance amplifier (OTA) for the high gain and low power neural recording frontend has been addressed in this paper. A novel split differential pair technique is proposed to improve the gain of the OTA without any additional bias current requirements. The design demonstrates a significant performance enhancement when compared to existing techniques, such as gain-boosting and recycling. A qualitative and quantitative treatment is presented to explore the impact of the split ratio on the performance parameters of gain, bandwidth, and linearity. A prototype implemented in TSMC 65 nm CMOS technology achieved 68 dB open loop-gain (13 dB higher than the conventional circuit) and a 17 kHz 3-dB bandwidth. A linearity of − 62 dB has been achieved with 7 mV pk–pk signal at the input. The circuit operates from a 1 V supply and draws 0.6 uA static current. The prototype occupies 3300 um2 silicon area

Simulation of driver fatigue monitoring via blink rate detection, using 65nm CMOS technology

This paper proposes a system to detect and measure blink rate to determine fatigue levels. The method involved analysing specific frames to determine that a blink occurred, and then monitoring the time between successive blinks. The program was simulated in python using a Raspberry Pi Zero and a standard USB camera. For the blink rate detection block, a gate level schematic was implemented in Cadence software using 65nm CMOS technology. The design was based around an asynchronous 6-bit based edge counter which was designed using D-flip-flops. The simulation calculated the average blink rate and compared this to the most recent blink rate. The outcome would determine if an alarm signal should be sent to the alarm. The system consumed 130uA from a 1.2V power supply

A 0.82V supply and 23.4 ppm/0C current mirror assisted bandgap reference

Traditional BGR circuits require a 1.05V supply due to the VBE of the BJT. Deep submicron CMOS technologies are limiting the supply voltage to less than 940mV. Hence there is a strong motivation to design them at lower supply voltages. The supply voltage limitation in conventional BGR is described qualitatively in this paper. Further, a current mirror-assisted technique has been proposed to enable BGR operational at 0.82V supply. A prototype was developed in 65nm TSMC CMOS technology and post-layout simulation results were performed. A self-bias opamp has been exploited to minimize the systematic offset. Proposed BGR targeted at 450mV works from 0.82-1.05V supply without having any degradation in the performance while keeping the integrated noise of 15.2µV and accuracy of 23.4ppm/0C. Further, the circuit consumes 21µW of power and occupies 73*32µm2 silicon area

A 261mV bandgap reference based on beta multiplier with 64ppm

In this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias was able to minimise threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed 0.9mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64ppm/0C. The proposed circuit consumed 5.04µW of power from a 0.45V power supply voltage. A prototype was implemented in 65nm CMOS technology occupying a 2888µm2 silicon area, with the nominal value of the reference at 261mV