Bridging the Testing Speed Gap: Design for Delay Testability

The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addresse

A programmable-load CMOS ring oscillator/inverter chain for propagation-delay measurements

A description is given of a test structure consisting of a combination of a ring oscillator and an inverter chain. The circuit can be used to carry out propagation delay measurements on two circuit types and under a number of load conditions. Full characterization only takes one test circuit. The elements of this structure are connected to a programmable load varying from a fan-in of 1 up to a fan-in of 15. In this way, the operating environment of the circuit can be simulated in hardware. The measurements can be carried out by means of a conventional automated digital measurement system providing AC and DC parametric measurement capabilities

A low-speed BIST framework for high-performance circuit testing

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addresse

Jitter and Decision-level Noise Separation in A/D Converters

Gaussian aperture jitter leads to a reduced SNR of A/D converters. Also other noise sources, faults and nonlinearities affect the digital output signal. A measurement setup for a new off-chip diagnosis method, which systematically separates the jitter-induced errors from the errors caused by these other factors, is described. Deterministic errors are removed via a subtracting technique. High-level ADC simulations and measurements have been carried out to determine relations between the size of the jitter or decision-level noise and the remaining random errors. By carrying out two tests at two different input frequencies and using the simulation results, errors induced by decision-level noise can be remove

Determining DfT Hardware by VHDL-AMS Fault Simulation for Biological Micro-Electronic Fluidic Arrays

The interest of microelectronic fluidic arrays for biomedical applications, like DNA determination, is rapidly increasing. In order to evaluate these systems in terms of required Design-for-Test structures, fault simulations in both fluidic and electronic domains are necessary. VHDL-AMS can be used successfully in this case. This paper shows a highly testable architecture of a DNA Bio-Sensing array, its basic sensing concept, fluidic modeling and sensitivity analysis. The overall VHDL-AMS fault simulation of the system is shown

On-Line Dependability Enhancement of Multiprocessor SoCs by Resource Management

This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation

Intermittent resistive faults in digital cmos circuits

A major threat in extremely dependable high-end process node integrated systems in e.g. Avionics are no failures found (NFF). One category of NFFs is the intermittent resistive fault, often originating from bad (e.g. Via or TSV-based) interconnections. This paper will show the impact of these faults on the behavior of a digital CMOS circuit via simulation. As the occurrence rate of this kind of defects can take e.g. One month, while the duration of the defect can be as short as 50 nanoseconds, to evoke and detect these faults is a huge scientific challenge. An on-chip data logging system with time stamp and stored environmental conditions, along with the detection, will drastically improve the task of maintenance of avionics and reduce the current high debugging costs

A Low Speed BIST Framework for High Speed Circuit Testing

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addresse

Plasmonic Cloaking of Cylinders: Finite Length, Oblique Illumination and Cross-Polarization Coupling

Metamaterial cloaking has been proposed and studied in recent years following several interesting approaches. One of them, the scattering-cancellation technique, or plasmonic cloaking, exploits the plasmonic effects of suitably designed thin homogeneous metamaterial covers to drastically suppress the scattering of moderately sized objects within specific frequency ranges of interest. Besides its inherent simplicity, this technique also holds the promise of isotropic response and weak polarization dependence. Its theory has been applied extensively to symmetrical geometries and canonical 3D shapes, but its application to elongated objects has not been explored with the same level of detail. We derive here closed-form theoretical formulas for infinite cylinders under arbitrary wave incidence, and validate their performance with full-wave numerical simulations, also considering the effects of finite lengths and truncation effects in cylindrical objects. In particular, we find that a single isotropic (idealized) cloaking layer may successfully suppress the dominant scattering coefficients of moderately thin elongated objects, even for finite lengths comparable with the incident wavelength, providing a weak dependence on the incidence angle. These results may pave the way for application of plasmonic cloaking in a variety of practical scenarios of interest.Comment: 17 pages, 11 figures, 2 table

Spectroscopy of a Cooper-Pair box in the Autler-Townes configuration

A theoretical spectroscopic analysis of a microwave driven superconducting charge qubit (Cooper-pair box coupled) to an RLC oscillator model is performed. By treating the oscillator as a probe through the backreaction effect of the qubit on the oscillator circuit, we extract frequency splitting features analogous to the Autler-Townes effect from quantum optics, thereby extending the analogies between superconducting and quantum optical phenomenology. These features are found in a frequency band that avoids the need for high frequency measurement systems and therefore may be of use in qubit characterization and coupling schemes. In addition we find this frequency band can be adjusted to suit an experimental frequency regime by changing the oscillator frequency.Comment: 13 pages, 7 figures. v2: Revised version after referee comments. Accepted for publication by Physical Review