Routing of guaranteed throughput traffic in a network-on-chip

This paper examines the possibilities of providing throughput guarantees in a network-on-chip by appropriate traffic routing. A source routing function is used to find routes with specified throughput for the data streams in a streaming multiprocessor system-on-chip. The influence of the routing algorithm, network topology and communication locality on the routing performance are studied. The results show that our method for providing throughput guarantees to streaming traffic is feasible. The communication locality has the strongest influence on the routing performance while the routing algorithm has weakest influence. Therefore, the mapping algorithm is of greater importance for the system performance than the routing algorithm and it is profitable to use a more complex mapping algorithm that preserves the communication locality together with a simple routing algorithm

A survey of efficient on-chip communications for SoC

This paper provides a survey of methods and techniques for flexible on-chip inter-processor communications for Systems-on-a-Chip (SoC) components. These devices are applied in battery-powered mobile multimedia devices. A classification is made of the most popular interconnection methods, techniques and mechanisms used for the inter-processor communications including interconnection network topologies, switching techniques, flow control, routing, deadlock avoidance and queuing techniques. Several projects dealing with on-chip interconnection networks are reviewed. As mobile multimedia devices are battery powered special attention is paid to energy-efficiency, the ways it can be achieved and how the different techniques contribute to it

Measuring workforce segregation: religious composition of private-sector employees at individual sites in Northern Ireland

This paper proposes a Network-on-Chip architecture that offers high flexibility and performance. It is used in a System-on-Chip platform for future multimedia mobile devices. The network is packet switching wormhole network with virtual-channel flow control and source routing. The initial implementation results for a network router show its feasibility and size comparable with other available solutions

Stream-processing pipelines: processing of streams on multiprocessor architecture

In this paper we study the timing aspects of the operation of stream-processing applications that run on a multiprocessor architecture. Dependencies are derived for the processing and communication times of the processors in such a system. Three cases of real-time constrained operation and four cases of communication organization are considered and compared. Examples of application are given for the derived results

A virtual channel router for on-chip networks

This paper proposes an architecture of a virtual channel router for an on-chip network1. The router has simple dynamic arbitration which is deterministic and fair. We show that the size of the proposed router is reduced by 49% and the speed increases 1.4 times compared to a conventional virtual channel router

Energy Model of Networks-on-Chip and a Bus

A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links