34 research outputs found

    Covalent Inhibitors of Human Monoacylglycerol Lipase: Ligand-Assisted Characterization of the Catalytic Site by Mass Spectrometry and Mutational Analysis

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    SummaryThe active site of recombinant hexa-histidine-tagged human monoacylglycerol lipase (hMGL) is characterized by mass spectrometry using the inhibitors 5-((biphenyl-4-yl)methyl)-N,N-dimethyl-2H-tetrazole-2-carboxamide (AM6701), and N-arachidonylmaleimide (NAM) as probes. Carbamylation of Ser129 by AM6701 in the putative hMGL catalytic triad demonstrates this residue's essential role in catalysis. Partial NAM alkylation of hMGL cysteine residues 215 and/or 249 was sufficient to achieve ∼80% enzyme inhibition. Although Cys215 and/or Cys249 mutations to alanine(s) did not affect hMGL hydrolytic activity as compared with nonmutated hMGL, the C215A displayed heightened NAM sensitivity, whereas the C249A evidenced reduced NAM sensitivity. These data conclusively demonstrate a sulfhydryl-based mechanism for NAM inhibition of hMGL in which Cys249 is of paramount importance. Identification of amino acids critical to the catalytic activity and pharmacological modulation of hMGL informs the design of selective MGL inhibitors as potential drugs

    Impact of Interconnect Advanced Patterning Options on Circuit Design

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    Optical lithography, the backbone of the industry for more than 50 years, has been pushing up against a number of physical barriers that have led to massive investments in development of alternative patterning techniques. Next generation lithography, based on extreme ultraviolet source (EUV), promises to overcome these issues, enabling the advancement into sub-32-nm nodes. However, EUV lithography has been confronted with a series of material and source issues, restricting its practical use for the semiconductor industry. Alternative advanced patterning options, such as multiple patterning (MP) for lines/spaces and directed self-assembly (DSA) for vias, offer significant improvements which allow the extension of conventional optical lithography down to sub-5-nm technology nodes. Multiple patterning options introduce variations in wire dimensions and spacing, while DSA vias require strict definition of the commensurable via grouping patterns in circuits. In this PhD, we aim to: a) analyze and evaluate the variability impact of the main variants of line/space MP on circuit design and performance, b) compare the results with next generation EUV lithography, c) provide a design solution for via patterning in advanced nodes, utilizing MP and templated DSA, and d) evaluate the provided solution with respect to its impact on circuit performance. In order to assess the impact of process variation, we developed a circuit-level variability analysis framework. We use this framework to generate statistical distributions of circuit performance metrics for logic circuits and SRAM arrays patterned with the considered MP options and EUV. Our results show a negligible impact of process variation related to MP options on the performance of logic circuits. This is not the case in SRAM arrays, where the impact can be substantial. For the via patterning, we propose a design method for DSA-aware via grouping and decomposition. Based on this method, we develop a fully parameterized EDA tool which can provide fast and efficient decomposition of any via layout into separate DSA-friendly masks. Running benchmark studies on a fully routed 32-bit processor, we demonstrate a drastic reduction in the number of masks per metal layer, providing a manufacturable solution with immersion ArF lithography. Finally, we show that the increased resistance variation in vias, introduced by the DSA process, has a negligible impact on circuit performance.nrpages: 210status: publishe

    Seminar: Layout decomposition algorithms for DSA via grouping

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    Design strategy for the integration of DSA vias in sub-7 nm circuits

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    Design strategy for layout of Sub-Resolution Directed Self-Assembly Assist Features (SDRAFs)

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    In the pursuit of alternatives to optical lithography, block copolymer directed self-assembly (DSA) has emerged as a low-cost, high-throughput option. DSA uses small topographical templates to contain the block copolymer and create small clusters of holes useful for patterning vias [1]. However, issues of defectivity have hampered DSA' s viability for large-scale patterning. Recent studies have shown polymer fill level to be a crucial factor in defectivity, as template overfill can result in malformed DSA structures [2]. The inherent density variations in via layouts, though, make regions of overfilled templates nearly inevitable, as templates in less dense regions will contain more polymer. For this reason, we develop a method to integrate sub-DSA resolution assist features (SDRAFs) into DSA template layouts. The SDRAFs divert excess polymer from the overfilled main templates but are themselves too small to form transferrable DSA patterns [2]. Thus, we can populate low-density regions with SDRAFs to make a layout more uniformly dense. To do this, we use SDRAFs with a set of lithography-based design rules dictating the minimum pitch and resist thickness between features (95 nm and 45 nm for 193i, respectively). The SDRAF CD is also chosen to be as large as possible without forming a transferrable DSA pattern, setting it at 40 nm for an L0 = 40 nm polymer and a PS wetting flow. With these rules, we set a flow for the assignment of each SDRAF according to the calculated density of templates in each block. We demonstrate the process on a 2.5 x 2.5 um section from V23 (the via layer connecting metals 2 and 3) of a routed N7 Cortex-M0 processor scaled to a 24 nm via layout grid. We first overlay the template layout with a grid of SDRAFs spaced at 96 nm, allowing the SDRAFs to align with the via grid. We then remove the SDRAFs that violate the minimum resist or pitch rules and assess the density result. This is done by dividing the layout into blocks and calculating the percentage of area occupied by the main and assist templates in the blocks, using prior experimental data for template area [3]. The size of the blocks is set to the length over which the polymer reflows during the thermal anneal [4], assumed here to be about 500 nm. Finally, the SDRAF grid is shifted vertically and horizontally in increments of the via grid (24 nm) to achieve different density results, as each shift causes different SDRAFs to be in violation. We can then choose the shift that minimizes the density variation across the blocks as the final layout. In our test case, we found that the density range of the blocks changed from 2.8-8.6% to 10.9-12.9% post-SDRAF assignment. Here, the polymer film thickness can be adjusted to accommodate the higher overall density and the narrowed density range shows promise to reduce template overfill. Future work will incorporate methods of improving the layout's PV band to create an SDRAF design strategy that is more DSA- and lithography-friendly. [1] H. Yi et al., Adv. Mater 24, 23 (2012). [2] H. Yi et al., Proc. SPIE 9423, 1F (2015). [3] J. Doise et al., J. Vac. Sci. Technol. B 33, 6 (2015). [4] H. Yi et al., Proc. SPIE 9323, 2A (2015).status: publishe

    Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits

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    Major advancements in the directed self-assembly (DSA) of block copolymers have shown the technique’s strong potential for via/contact layer patterning in advanced technology nodes. Molecular scale pattern precision along with low cost processing promotes DSA technology as a great candidate for complementing conventional photolithography. Our studies show that decomposition of via layers with 193-nm immersion lithography in realistic circuits below the 7-nm node would require a prohibitive number of multiple patterning steps. The grouping of vias through templated DSA can resolve local conflicts in high density areas, limiting the number of required masks, and thus cutting a great deal of the associated costs. A design method for DSA via patterning in sub-7-nm nodes is discussed. We present options to expand the list of usable DSA templates and we formulate cost functions and algorithms for the optimal DSA-aware via layout decomposition. The proposed method works a posteriori, after place-and-route, allowing for fast practical implementation. We tested this method on a fully routed 32-bit processor designed for sub-7 nm technology nodes. Our results demonstrate a reduction of up to four lithography masks when compared to conventional non-DSA-aware decomposition.status: publishe
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