Impact of Interconnect Advanced Patterning Options on Circuit Design

Abstract

Optical lithography, the backbone of the industry for more than 50 years, has been pushing up against a number of physical barriers that have led to massive investments in development of alternative patterning techniques. Next generation lithography, based on extreme ultraviolet source (EUV), promises to overcome these issues, enabling the advancement into sub-32-nm nodes. However, EUV lithography has been confronted with a series of material and source issues, restricting its practical use for the semiconductor industry. Alternative advanced patterning options, such as multiple patterning (MP) for lines/spaces and directed self-assembly (DSA) for vias, offer significant improvements which allow the extension of conventional optical lithography down to sub-5-nm technology nodes. Multiple patterning options introduce variations in wire dimensions and spacing, while DSA vias require strict definition of the commensurable via grouping patterns in circuits. In this PhD, we aim to: a) analyze and evaluate the variability impact of the main variants of line/space MP on circuit design and performance, b) compare the results with next generation EUV lithography, c) provide a design solution for via patterning in advanced nodes, utilizing MP and templated DSA, and d) evaluate the provided solution with respect to its impact on circuit performance. In order to assess the impact of process variation, we developed a circuit-level variability analysis framework. We use this framework to generate statistical distributions of circuit performance metrics for logic circuits and SRAM arrays patterned with the considered MP options and EUV. Our results show a negligible impact of process variation related to MP options on the performance of logic circuits. This is not the case in SRAM arrays, where the impact can be substantial. For the via patterning, we propose a design method for DSA-aware via grouping and decomposition. Based on this method, we develop a fully parameterized EDA tool which can provide fast and efficient decomposition of any via layout into separate DSA-friendly masks. Running benchmark studies on a fully routed 32-bit processor, we demonstrate a drastic reduction in the number of masks per metal layer, providing a manufacturable solution with immersion ArF lithography. Finally, we show that the increased resistance variation in vias, introduced by the DSA process, has a negligible impact on circuit performance.nrpages: 210status: publishe