Ovonic threshold-switching GexSey chalcogenide materials : stoichiometry, trap nature, and material relaxation from first principles

Density functional theory simulations are used to identify the structural factors that define the material properties of ovonic threshold switches (OTS). They show that the nature of mobility-gap trap states in amorphous Ge-rich Ge50Se50 is related to Ge-Ge bonds, whereas in Se-rich Ge30Se70 the Ge valence-alternating-pairs and Se lone-pairs dominate. To obtain a faithful description of the electronic structure and delocalization of states, it is required to combine hybrid exchange-correlation functionals with large unit-cell models. The extent of localization of electronic states depends on the applied external electric field. Hence, OTS materials undergo structural changes during electrical cycling of the device, with a decrease in the population of less exothermic Ge-Ge bonds in favor of more exothermic Ge-Se. This reduces the amount of charge traps, which translates into coordination changes, an increase in mobility-gap, and subsequently changes in the selector-device electrical parameters. The threshold voltage drift process can be explained by natural evolution of the nonpreferred Ge-Ge bonds (or "chains"/clusters thereof) in Ge-rich GexSe1-x. The effect of extrinsic doping is shown for Si and N, which introduce strong covalent bonds into the system, increase both mobility-gap and crystallization temperature, and decrease the leakage current

Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM

Understanding the defects in magnetic tunnel junctions (MTJs) and their faulty behaviors are paramount for developing high-quality tests for STT-MRAM. This paper characterizes and models intermediate (IM) state defects in MTJs; IM state manifests itself as an abnormal third resistive state, apart from the two bi-stable states of MTJ. We performed silicon measurements on MTJ devices with diameter ranging from 60 nm to 120 nm; the results reveal that the occurrence probability of IM state strongly depends on the switching direction, device size, and applied bias voltage. To test such defect, appropriate fault models are needed. Therefore, we use the advanced device-aware modeling approach, where we first physically model the defect and incorporate it into a Verilog-A MTJ compact model and calibrate it with silicon data. Thereafter, we use a systematic fault analysis to accurately validate a theoretically predefined fault space and derive realistic fault models. Our simulation results show that the IM state defect causes intermittent write transition faults. This paper also demonstrates that the conventional resistor-based fault modeling and test approach fails in appropriately modeling IM defects, and hence incapable of detecting such defects

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs

Understanding the manufacturing defects in magnetic tunnel junctions (MTJs), which are the data-storing elements in STT-MRAMs, and their resultant faulty behaviors are crucial for developing high-quality test solutions. This paper introduces a new type of MTJ defect: synthetic anti-ferromagnet flip (SAFF) defect, wherein the magnetization in both the hard layer and reference layer of MTJ devices undergoes an unintended flip to the opposite direction. Both magnetic and electrical measurement data of SAFF defect in fabricated MTJ devices is presented; it shows that such a defect reverses the polarity of stray field at the free layer of MTJ, while it has no electrical impact on the single isolated device. The paper also demonstrates that using the conventional fault modeling and test approach fails to appropriately model and test such a defect. Therefore device-Aware fault modeling and test approach is used. It first physically models the defect and incorporate it into a Verilog-A MTJ compact model, which is afterwards calibrated with silicon data. The model is thereafter used for fault analysis and modeling within an STT-MRAM array; simulation results show that a SAFF defect may lead to an intermittent Passive Neighborhood Pattern Sensitive Fault (PNPSF1i) when all neighboring cells are in logic '1' state. Finally, test solutions for such fault are discussed.</p

Interplay of Voltage Control of Magnetic Anisotropy, Spin-Transfer Torque, and Heat in the Spin-Orbit-Torque Switching of Three-Terminal Magnetic Tunnel Junctions

We use three-terminal magnetic tunnel junctions (MTJs) designed for field-free switching by spin-orbit torques (SOTs) to systematically study the impact of dual voltage pulses on the switching performance. We show that the concurrent action of an SOT pulse and an MTJ bias pulse allows for reducing the critical switching energy below the level typical of spin-transfer-torque while preserving the ability to switch the MTJ on the subnanosecond time scale. By performing dc and real-time electrical measurements, we discriminate and quantify three effects arising from the MTJ bias: the voltage-controlled change of the perpendicular magnetic anisotropy, current-induced heating, and the spin-transfer torque. The experimental results are supported by micromagnetic modeling. We observe that, depending on the pulse duration and the MTJ diameter, different effects take a lead in assisting the SOTs in the magnetization-reversal process. Finally, we present a compact model that allows for evaluating the impact of each effect due to the MTJ bias on the critical switching parameters. Our results provide input to optimize the switching of three-terminal devices as a function of time, size, and material parameters.ISSN:2331-701

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs

Understanding the manufacturing defects in magnetic tunnel junctions (MTJs), which are the data-storing elements in STT-MRAMs, and their resultant faulty behaviors are crucial for developing high-quality test solutions. This paper introduces a new type of MTJ defect: synthetic anti-ferromagnet flip (SAFF) defect, wherein the magnetization in both the hard layer and reference layer of MTJ devices undergoes an unintended flip to the opposite direction. Both magnetic and electrical measurement data of SAFF defect in fabricated MTJ devices is presented; it shows that such a defect reverses the polarity of stray field at the free layer of MTJ, while it has no electrical impact on the single isolated device. The paper also demonstrates that using the conventional fault modeling and test approach fails to appropriately model and test such a defect. Therefore device-Aware fault modeling and test approach is used. It first physically models the defect and incorporate it into a Verilog-A MTJ compact model, which is afterwards calibrated with silicon data. The model is thereafter used for fault analysis and modeling within an STT-MRAM array; simulation results show that a SAFF defect may lead to an intermittent Passive Neighborhood Pattern Sensitive Fault (PNPSF1i) when all neighboring cells are in logic '1' state. Finally, test solutions for such fault are discussed.Computer EngineeringQuantum & Computer Engineerin

MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design

The popularity of perpendicular magnetic tunnel junction (pMTJ)-based spin-transfer torque magnetic random access memories (STT-MRAMs) is growing very fast. The performance of such memories is very sensitive to magnetic fields, including both internal and external ones. This article presents a magnetic-field-aware compact model of pMTJ, named the MFA-magnetic tunnel junction (MTJ) model, for magnetic/electrical co-simulation of MTJ/CMOS circuits. Magnetic measurement data of MTJ devices, with diameters ranging from 35 to 175 nm, are used to calibrate an in-house magnetic coupling model. This model is subsequently integrated into our developed compact pMTJ model, which is implemented in Verilog-A. The superiority of the proposed MFA-MTJ model for device/circuit co-design of STT-MRAM is demonstrated by simulating a single pMTJ as well as STT-MRAM full circuits. The design space is explored under PVT variations and various configurations of magnetic fields.Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Computer EngineeringQuantum & Computer Engineerin

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs

The manufacturing process of STT-MRAM requires unique steps to fabricate and integrate magnetic tunnel junction (MTJ) devices which are data-storing elements. Thus, understanding the defects in MTJs and their faulty behaviors are paramount for developing high-quality test solutions. This article applies the advanced device-aware test to intermediate (IM) state defects in MTJ devices based on silicon measurements and circuit simulations. An IM state manifests itself as an abnormal third resistive state, which differs from the two bi-stable states of MTJ. We performed silicon measurements on MTJ devices with diameter ranging from 60nm to 120nm; the results show that the occurrence probability of IM state strongly depends on the switching direction, device size, and bias voltage. We demonstrate that the conventional resistor-based fault modeling and test approach fails to appropriately model and test such a defect. Therefore, device-aware test is applied. We first physically model the defect and incorporate it into a Verilog-A MTJ compact model and calibrate it with silicon data. Thereafter, this model is used for a systematic fault analysis based on circuit simulations to obtain accurate and realistic faults in a pre-defined fault space. Our simulation results show that an IM state defect leads to intermittent write transition faults. Finally, we propose and implement a device-aware test solution to detect the IM state defect.Computer EngineeringQuantum & Computer Engineerin

Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM

Understanding the defects in magnetic tunnel junctions (MTJs) and their faulty behaviors are paramount for developing high-quality tests for STT-MRAM. This paper characterizes and models intermediate (IM) state defects in MTJs; IM state manifests itself as an abnormal third resistive state, apart from the two bi-stable states of MTJ. We performed silicon measurements on MTJ devices with diameter ranging from 60 nm to 120 nm; the results reveal that the occurrence probability of IM state strongly depends on the switching direction, device size, and applied bias voltage. To test such defect, appropriate fault models are needed. Therefore, we use the advanced device-aware modeling approach, where we first physically model the defect and incorporate it into a Verilog-A MTJ compact model and calibrate it with silicon data. Thereafter, we use a systematic fault analysis to accurately validate a theoretically predefined fault space and derive realistic fault models. Our simulation results show that the IM state defect causes intermittent write transition faults. This paper also demonstrates that the conventional resistor-based fault modeling and test approach fails in appropriately modeling IM defects, and hence incapable of detecting such defects.Computer EngineeringQuantum & Computer Engineerin

Structural and Magnetic Properties of Mn3Ge Grown on a Thin Polycrystalline MgO Seed Layer

status: publishe