Analysis of Potential and Electron Density Behaviour in Extremely Scaled Si and InGaAs MOSFETs Applying Monte Carlo Simulations

Scaling of Silicon and InGaAs MOSFETs of a 25 nm gate length till shortest gate length of 5 nm, simulated this nano-device by Monte Carlo (MC) with quantum corrections. The transistors are scaled-down only in lateral dimensions in order to study electron transport approaching a ballistic limit along the scaled channel following experimental works. These MC simulations are able to give detailed insight into physical behaviour of electron velocity, electron density, and potential in relation to the drive current. We found that electron peak velocity increases during the scaling in Si MOSFETs till the 10 nm gate length and then dramatically declines due to a strong long-range Coulomb interaction among the source and the drain [16]. This effect is not observed in the equivalent InGaAs MOSFETs in which electron peak velocity exhibits double peak which steadily increases during the scaling [16]. However, the increasing of current in the equivalent InGaAs MOSFETs is moderate, by about 24 %, by comparing of current in the Si MOSFETs of 74 % delivered by 5 nm channel transistor

Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes

We investigate the performance and scalability of III-V-OI In0.53Ga0.47As and SOI Si FinFETs using state-of-the-art in-house-built 3D simulation tools. Three different technology nodes specified in the ITRS have been analysed with gate lengths (L G) of 14.0 nm, 12.8 and 10.4 nm for the InGaAs FinFETs and 12.8 nm, 10.7 and 8.1 nm for the Si devices. At a high drain bias, the 12.8 and 10.4 nm InGaAs FinFETs deliver 15% and 13% larger on-currents but 14% larger off-currents than the equivalent 12.8 and 10.7 nm Si FinFETs, respectively. For equivalent gate lengths, both the InGaAs and the Si FinFETs have the same I ON/I OFF ratio (5.9 × 104 when L G = 12.8 nm and 5.7 × 104 when L G = 10.4(10.7) nm). A more pronounced S/D tunnelling affecting the InGaAs FinFETs leads to a larger deterioration in their SS (less than 10%) and DIBL (around 20%) compared to the Si counterparts

Impact of Cross-Sectional Shape on 10-nm Gate Length InGaAs FinFET Performance and Variability

Three cross sections (rectangular, bullet shaped, and triangular), resulting from the fabrication process, of nanoscale In0.53Ga0.47As-on-insulator FinFETs with a gate length of 10.4 nm are modeled using in-house 3-D finite-element density-gradient quantum-corrected drift–diffusion and Monte Carlo simulations. We investigate the impact of the shape on I – V characteristics and on the variability induced by metal grain granularity (MGG), line-edge roughness (LER), and random dopants (RDs) and compared with their combined effect. The more triangular the cross section, the lower the OFF-current, the drain-induced-barrier-lowering, and the subthreshold slope. The ION/IOFF ratio is three times higher for the triangular-shaped FinFET than for the rectangular-shape one. Independent of the cross section, the MGG variations are the preeminent fluctuations affecting the FinFETs, with four to two times larger σVT than that from the LER and the RDs, respectively. However, the variability induced threshold voltage ( VT ) shift is minimal for the MGG (around 2 mV), but VT shift increases 4-fold and 15-fold for the LER and the RDs, respectively. The cross-sectional shape has a very small influence in VT and OFF-current of the MGG, LER, and RD variabilities, both separated and in combination, with standard deviation differences of only 4% among the different device shapes. Finally, the statistical sum of the three sources of variability can predict simulated combined variability with only a minor overestimation

Buffer Trap Related Knee Walkout and the Effects of Self-Heating in AlGaN/GaN HEMTs

Mixed-mode simulations of a class A amplifier is used to study the DC/RF dispersion commonly observed in AlGaN/GaN based HEMTs. We show that the observed knee walkout at frequencies greater than the emission rates of buffer traps (time constants tae > 1 week) is related to the steady state trap density and spatial location due to the DC operational bias. An increase in the drain bias point and an initial distortion of the RF signal, that is expected to disappear as the device global temperature reduces, is observed when a self-heating model is included. Finally, we propose that a reduction in the DC/RF dispersion is possible with a suitable location and concentration of an acceptor doping in the buffer

Fluctuation Sensitivity Map: A Novel Technique to Characterise and Predict Device Behaviour Under Metal Grain Work-Function Variability Effects

A new technique developed for the analysis of intrinsic sources of variability affecting the performance of semiconductor devices is presented. It is based on the creation of a fluctuation sensitivity map (FSM), which supplies spatial information about the source of variability affecting the device performance and reliability, providing useful advice in the development of fluctuation-resistant device architectures. We have applied the FSM to metal grain work-function variations (MGWVs), since they are one of the major contributors to device variability. This technique is computationally very efficient because, once the original FSM is created, it can be used to predict the MGWV for different metal gates or grain sizes (GSs). Two state-of-the-art devices were used as test-models: a 10.7-nm gate length Si FinFET and 10.4-nm gate length In0.53Ga0.47As FinFET. The cross-sectional shape (triangular, rectangular, or bullet), the metal used in the gate (TiN or WN), and the GS (10, 7, and 5 nm) have been used as test scenarios for this technique

Multilevel 3-D Device Simulation Approach Applied to Deeply Scaled Nanowire Field Effect Transistors

Three silicon nanowire (SiNW) field effect transistors (FETs) with 15 -, 12.5 -and 10.6 -nm gate lengths are simulated using hierarchical multilevel quantum and semiclassical models verified against experimental ID – VG characteristics. The tight-binding (TB) formalism is employed to obtain the band structure in k -space of ellipsoidal NWs to extract electron effective masses. The masses are transferred into quantum-corrected 3-D finite element (FE) drift-diffusion (DD) and ensemble Monte Carlo (MC) simulations, which accurately capture the quantum-mechanical confinement of the ellipsoidal NW cross sections. We demonstrate that the accurate parameterization of the bandstructure and the quantum-mechanical confinement has a profound impact on the computed ID – VG characteristics of nanoscaled devices. Finally, we devise a step-by-step technology computer-aided design (TCAD) methodology of simple parameterization for efficient DD device simulations

Simulations of Statistical Variability in n-Type FinFET, Nanowire, and Nanosheet FETs

Four sources of variability, metal grain granularity (MGG), line-edge roughness (LER), gate-edge roughness (GER), and random discrete dopants (RDD), affecting the performance of state-of-the-art FinFET, nanosheet (NS), and nanowire (NW) FETs, are analysed via our in-house 3D finite-element drift-diffusion/Monte Carlo simulator that includes 2D Schrödinger equation quantum corrections. The MGG and LER are the sources of variability that influence device performance of the three multi-gate architectures the most. The FinFET and the NS FET are similarly affected by the MGG variations with threshold voltage and on-current standard deviations significantly lower (at least 20 %) than those of the NW FET. The LER variability has a negligible influence in the NS FET performance with σVT values around 12 and 42 times lower than those of the FinFET and the NW FET. The three architectures are equally affected by the RDD (σVT= 8 mV) and minimally influenced by the GER (σVT ≈ 4 mV). The variability of NS FETs makes them strong candidates to replace FinFETs

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length ( LG ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to LG of 16 nm offering a larger on-current ( ION ) and slightly better sub-threshold characteristics. Below LG of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current ( IOFF ), and the largest ION/IOFF ratio out of the three architectures. However, the NW FET suffers from early ION saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body