A low-power transmission-gate-based 16-bit multiplier for digital hearing aids

The most widespread 16-bit multiplier architectures are compared in terms of area occupation, dissipated energy, and EDP (Energy-Delay Product) in view of low-power low-voltage signal processing for digital hearing aids and similar applications. Transistor-level simulations including back-annotated wire parasitics confirm that the propagation of glitches along uneven and re-convergent paths results in large unproductive node activity. Because of their shorter full-adder chains, Wallace-tree multipliers indeed dissipate less energy than the carry-save (CSM) and other traditional array multipliers (6.0µW/MHz versus 10.9µW/MHz and more for 0.25µm CMOS technology at 0.75V). By combining the Wallace-tree architecture with transmission gates (TGs), a new approach is proposed to improve the energy efficiency further (3.1µW/MHz), beyond recently published low-power architectures. Besides the reduction of the overall capacitance, minimum-sized transmission gate full-adders act as RC-low-pass filters that attenuate undesired switching. Finally, minimum size TGs increase the V dd to ground resistance, hence decreasing leakage dissipation (0.55nW versus 0.84nW in CSM and 0.94nW in Wallace

Design of plasmonic-waveguiding structures for sensor applications

Surface plasmon resonance has become a widely accepted optical technique for studying biological and chemical interactions. Among others, detecting small changes in analyte concentration in complex solutions remains challenging, e.g., because of the need of distinguishing the interaction of interest from other effects. In our model study, the resolution ability of plasmonic sensing element was enhanced by two ways. Besides an implementation of metal-insulator-metal (MIM) plasmonic nanostructure, we suggest concatenation with waveguiding substructure to achieve mutual coupling of surface plasmon polariton (SPP) with an optical waveguiding mode. The dependence of coupling conditions on the multilayer parameters was analyzed to obtain optimal field intensity enhancement.Web of Science99art. no. 122

Cell-Based Multilevel Carry-Increment Adders with Minimal AT- and PT-Products

Carry-select addition techniques imply the computation of double sum and carry bits with subsequent selection of the correct values, resulting in significant area overheads. This overhead increases massively when the selection scheme is applied to multiple levels in order to further reduce computation time. A recently proposed reduced-area scheme for carry-select adders lowers this overhead by computing the carry and sum bits for a block-carry-in value of 0 only and by incrementing them afterwards depending on the final block-carry-in. The resulting carry-increment adder cuts circuit size down by 23% with no change in performance. This paper extends this increment scheme hierarchically to build multilevel carry-increment adders. It is shown that such adders are considerably faster while maintaining the same area complexity. The implemented 2-level carry-increment adder has roughly the same size as the 1-level version, but is up to 29% faster. For large word lengths (up to 128 bits), it..