A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient Computing

Kaiser M, Griessl R, Hagemeyer J, et al. A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient Computing. In: Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC'17). Denver, CO; 2017

Optimizing inter-FPGA communication by automatic channel adaptation

Romoth J, Jungewelter D, Hagemeyer J, Porrmann M, Rückert U. Optimizing inter-FPGA communication by automatic channel adaptation. In: 2012 International Conference on Reconfigurable Computing and FPGAs. 5 - 7 Dec. 2012, Cancun, Mexico . Piscataway, NJ: IEEE; 2012: 1-7.Tightly coupled multi-FPGA architectures gain more and more interest in various application areas, like prototyping MPSoC, code breaking, or artificial neural networks, just to name a few. Communication protocols and implementations have to deal with rising clock frequencies on the one hand and short time to market demands on the other hand. These tight schedules and limited routing areas often lead to PCB routing which is not ideal in terms of length matching and therefore introduces different delays in parallel transmission lines. Crosstalk, impedance mismatch, and jitter further deteriorate the quality of the received signal. In order to achieve optimum data rates modern FPGAs offer different mechanisms to adapt to the behavior of the channel. This paper introduces a communication protocol and an architecture which evaluates the channel delays and automatically generates the configuration for the different mechanisms offered by the used FPGAs. The protocol supports several transmission standards and can be scaled to different physical and virtual channel widths

AXI-based SpaceFibre IP CORE Implementation

Cozzi D, Jungewelter D, Kleibrink D, et al. AXI-based SpaceFibre IP CORE Implementation. Presented at the 6th International SpaceWire Conference, Athens, Greece

An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems

Cassano L, Cozzi D, Jungewelter D, et al. An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems. Presented at the DTIS 2014, 9th International conference on Design & Technology of Integrated Systems in Nanoscale Era, Santorini , Greece