Unveiling the Real Performance of LPDDR5 Memories

LPDDR5 is the latest low-power DRAM standard and expected to be used in various application fields. The vendors have published promising peak bandwidths up to 50 % higher than those of the predecessor LPDDR4. In this paper we evaluate the best-case and worst-case real bandwidth utilization of different LPDDR5 configurations and compare the results to corresponding LPDDR4 configurations. We also show that an upgrade from LPDDR4 to LPDDR5 does not always bring a bandwidth advantage and that some LPDDR5 configurations should be avoided for specific workloads.Comment: ACM/IEEE International Symposium on Memory Systems (MEMSYS 2022

Optimization of the Memory Subsystem of a Coarse Grained Reconfigurable Hardware Accelerator

Fast and energy efficient processing of data has always been a key requirement in processor design. The latest developments in technology emphasize these requirements even further. The widespread usage of mobile devices increases the demand of energy efficient solutions. Many new applications like advanced driver assistance systems focus more and more on machine learning algorithms and have to process large data sets in hard real time. Up to the 1990s the increase in processor performance was mainly achieved by new and better manufacturing technologies for processors. That way, processors could operate at higher clock frequencies, while the processor microarchitecture was mainly the same. At the beginning of the 21st century this development stopped. New manufacturing technologies made it possible to integrate more processor cores onto one chip, but almost no improvements were achieved anymore in terms of clock frequencies. This required new approaches in both processor microarchitecture and software design. Instead of improving the performance of a single processor, the current problem has to be divided into several subtasks that can be executed in parallel on different processing elements which speeds up the application. One common approach is to use multi-core processors or GPUs (Graphic Processing Units) in which each processing element calculates one subtask of the problem. This approach requires new programming techniques and legacy software has to be reformulated. Another approach is the usage of hardware accelerators which are coupled to a general purpose processor. For each problem a dedicated circuit is designed which can solve the problem fast and efficiently. The actual computation is then executed on the accelerator and not on the general purpose processor. The disadvantage of this approach is that a new circuit has to be designed for each problem. This results in an increased design effort and typically the circuit can not be adapted once it is deployed. This work covers reconfigurable hardware accelerators. They can be reconfigured during runtime so that the same hardware is used to accelerate different problems. During runtime, time consuming code fragments can be identified and the processor itself starts a process that creates a configuration for the hardware accelerator. This configuration can now be loaded and the code will then be executed on the accelerator faster and more efficient. A coarse grained reconfigurable architecture was chosen because creating a configuration for it is much less complex than creating a configuration for a fine grained reconfigurable architecture like an FPGA (Field Programmable Gate Array). Additionally, the smaller overhead for the reconfigurability results in higher clock frequencies. One advantage of this approach is that programmers don't need any knowledge about the underlying hardware, because the acceleration is done automatically during runtime. It is also possible to accelerate legacy code without user interaction (even when no source code is available anymore). One challenge that is relevant for all approaches, is the efficient and fast data exchange between processing elements and main memory. Therefore, this work concentrates on the optimization of the memory interface between the coarse grained reconfigurable hardware accelerator and the main memory. To achieve this, a simulator for a Java processor coupled with a coarse grained reconfigurable hardware accelerator was developed during this work. Several strategies were developed to improve the performance of the memory interface. The solutions range from different hardware designs to software solutions that try to optimize the usage of the memory interface during the creation of the configuration of the accelerator. The simulator was used to search the design space for the best implementation. With this optimization of the memory interface a performance improvement of 22.6% was achieved. Apart from that, a first prototype of this kind of accelerator was designed and implemented on an FPGA to show the correct functionality of the whole approach and the simulator

A Framework for Formal Verification of DRAM Controllers

The large number of recent JEDEC DRAM standard releases and their increasing feature set makes it difficult for designers to rapidly upgrade the memory controller IPs to each new standard. Especially the hardware verification is challenging due to the higher protocol complexity of standards like DDR5, LPDDR5 or HBM3 in comparison with their predecessors. With traditional simulation-based verification it is laborious to guarantee the coverage of all possible states, especially for control flow rich memory controllers. This has a direct impact on the time-to-market. A promising alternative is formal verification because it allows to ensure protocol compliance based on mathematical proofs. However, with regard to memory controllers no fully-automated verification process has been presented in the state-of-the-art yet, which means there is still a potential risk of human error. In this paper we present a framework that automatically generates SystemVerilog Assertions for a DRAM protocol. In addition, we show how the framework can be used efficiently for different tasks of memory controller development.Comment: ACM/IEEE International Symposium on Memory Systems (MEMSYS 2022

Информационная система технического сервиса машинотракторного парка

Предоставление услуг технического сервиса требует предоставления гарантий качества этих услуг. Результаты исследований ведущих специалистов в этой области не всегда доступны инженерам сельскохозяйственных предприятий, поэтому существует необходимость в разработке методик оценки качества клиентом или подтверждения обеспечения качества поставщиком услуг технического сервиса. Проект системы технического сервиса машинотракторного парка, включающей в себя совокупность взаимосвязанных и взаимообусловленных ее элементов - процессов, происходящих в машинах; технологий технического сервиса; исполнителей технического сервиса - определяемую и направляемую целью технического сервиса - поддержание работоспособности сельскохозяйственной техники, позволяет сформировать методику оценки качества. Показатель качества представляет собой произведение частных коэффициентов, учитывающих степень соответствия выполненных объемов работ требуемым объемам; степень соответствия периодичности ТО требуемым значениям; степень соответствия технологий ТО и ремонта процессам в подсистемах; достаточность компетенций исполнителей для реализации технологий ТО и ремонта; достаточность перечня работ, потенциально выполняемых исполнителями технического сервиса, для обслуживания определенного вида машинотракторных агрегатов. Степень соответствия периодичности может обеспечиваться соблюдением требований нормативно-технической документации. Объемы работ технического сервиса могут быть обеспечены работой группы исполнителей технического сервиса. Предлагается вариант методики оценки компетенций исполнителей технического сервиса. Вместе с тем разработанная информационная система технического сервиса позволяет выявить взаимосвязи, определяющие качество технического сервиса.Providing technical services also requires providing quality assurance of these services. Results of leading experts' research in this field is not always available for engineers of agricultural companies, that is why there is need for development of a customer quality assessment method or a method of quality assurance by technical services suppliers. Project of machines and tractor fleet technical service system which included an assembly of interrelated and interdependent elements - processes running in machines, technologies of technical service, performers of technical service - is defined and directed by the aim of technical service which consists in maintaining operability of agricultural equipment, allows to create a method of quality assessment. The quality index represents multiplication of partial factors which take into consideration degree of correspondence of performed volume of works to the required volume, degree of correspondence of maintenance intervals to the required intervals, degree of conformity of repair and maintenance technologies to processes in subsystems; sufficiency of performers competence for implementation of repair and maintenance; sufficiency of range of works potentially carried out by technical service performers for maintenance of a certain types of machine- and tractor aggregates. The degree of correspondence of intervals can be ensured by meeting the requirements of standards and technical documentation. The volume of technical services works can be provided by involving a group of technical service performers. A variant of technical service performers' competence assessment method is suggested. Along with that an information system of technical service is developed which allows to state interdependencies determining quality of technical service

Accurate structure models and absolute configuration determination using dynamical effects in continuous-rotation 3D electron diffraction data

Continuous-rotation 3D electron diffraction methods are increasingly popular for the structure analysis of very small organic molecular crystals and crystalline inorganic materials. Dynamical diffraction effects cause non-linear deviations from kinematical intensities that present issues in structure analysis. Here, a method for structure analysis of continuous-rotation 3D electron diffraction data is presented that takes multiple scattering effects into account. Dynamical and kinematical refinements of 12 compounds—ranging from small organic compounds to metal–organic frameworks to inorganic materials—are compared, for which the new approach yields significantly improved models in terms of accuracy and reliability with up to fourfold reduction of the noise level in difference Fourier maps. The intrinsic sensitivity of dynamical diffraction to the absolute structure is also used to assign the handedness of 58 crystals of 9 different chiral compounds, showing that 3D electron diffraction is a reliable tool for the routine determination of absolute structures. [Figure not available: see fulltext.]