Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications

Multiple Input Energy Harvesting Systems for Autonomous IoT End-Nodes

The Internet-of-Things (IoT) paradigm is under constant development and is being enabled by the latest research work from both industrial and academic communities. Among the many contributions in such diverse areas as sensor manufacturing, network protocols, and wireless communications, energy harvesting techniques stand out as a key enabling technology for the realization of batteryless IoT end-node systems. In this paper, we give an overview of the recent developments in circuit design for ultra-low power management units (PMUs), focusing mainly in the architectures and techniques required for energy harvesting from multiple heterogeneous sources. The paper starts by discussing a general structure for IoT end-nodes and the main characteristics of PMUs for energy harvesting. Then, an overview is given of different published works for multisource power harvesting, observing their main advantages and disadvantages and comparing their performance. Finally, some open areas of research in multisource harvesting are observed and relevant conclusions are given

Skew-Circulant-Matrix-Based Harmonic-Canceling Synthesizer for BIST Applications

Testing is an important part of the design flow in the semiconductor industry. Unfortunately, it also consumes up to half of the production cost. On-silicon stimulus generators and response analyzers can be integrated with the Device-Under-Test (DUT) to reduce production costs with a minimum increment in power and area consumption. This practice is known as the Built-In Self-Test (BIST). This work presents a single-tone generator for BIST applications that is based on the Harmonic-Canceling (HC) technique. The main idea is to cancel or filter out the harmonics of a square-wave signal in order to obtain a highly pure sine wave. The design challenges of this technique are the precise implementation of irrational coefficients in silicon and the strong dependence of the output’s linearity on the coefficients’ precision. In order to reduce this dependence, this work introduces an irrational coefficient generator that is based on the recursive use of special matrices called skew-circulant matrices (SCMs). A complete study of the SCM-based HC synthesizer, its properties, and the proposed implementation in 180 nm CMOS technology are presented. The measured results show that the proposed HC synthesizer is able to filter out up to the 47th harmonic of a given square wave and to generate signals from 0.8 to 100 MHz with a maximum Spurious-Free Dynamic Range (SFDR) of 66 dB

Skew-Circulant-Matrix-Based Harmonic-Canceling Synthesizer for BIST Applications

Testing is an important part of the design flow in the semiconductor industry. Unfortunately, it also consumes up to half of the production cost. On-silicon stimulus generators and response analyzers can be integrated with the Device-Under-Test (DUT) to reduce production costs with a minimum increment in power and area consumption. This practice is known as the Built-In Self-Test (BIST). This work presents a single-tone generator for BIST applications that is based on the Harmonic-Canceling (HC) technique. The main idea is to cancel or filter out the harmonics of a square-wave signal in order to obtain a highly pure sine wave. The design challenges of this technique are the precise implementation of irrational coefficients in silicon and the strong dependence of the output’s linearity on the coefficients’ precision. In order to reduce this dependence, this work introduces an irrational coefficient generator that is based on the recursive use of special matrices called skew-circulant matrices (SCMs). A complete study of the SCM-based HC synthesizer, its properties, and the proposed implementation in 180 nm CMOS technology are presented. The measured results show that the proposed HC synthesizer is able to filter out up to the 47th harmonic of a given square wave and to generate signals from 0.8 to 100 MHz with a maximum Spurious-Free Dynamic Range (SFDR) of 66 dB

Design Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers

Fully differential amplifiers require the use of common-mode feedback (CMFB) circuits to properly set the amplifier’s operating point. Due to scaling trends in CMOS technology, modern amplifiers increasingly rely on cascading more than two stages to achieve sufficient gain. With multiple gain stages, different topologies for implementing CMFB are possible, whether using a single CMFB loop or multiple ones. However, the impact on performance of each CMFB approach has seldom been studied in the literature. The aim of this work is to guide the choice of the CMFB implementation topology evaluating performance in terms of stability, linearity, noise and common-mode rejection. We present a detailed theoretical analysis, comparing the relative performance of two CMFB configurations for 3-stage OTA topologies in an implementation-agnostic manner. Our analysis is then corroborated through a case study with full simulation results comparing the two topologies at the transistor level and confirming the theoretical intuition. An active-RC filter is used as an example of a high-linearity OTA application, highlighting a 6 dB improvement in P1dB in the multi-loop implementation with respect to the single-loop case

An Accurate UAV Ground Landing Station System Based on BLE-RSSI and Maximum Likelihood Target Position Estimation

Earth observation with unmanned aerial vehicles (UAVs) offers an extraordinary opportunity to bridge the gap between field observations and traditional air and space-borne remote sensing. In this regard, ground landing stations (GLS) systems play a central role to increase the time and area coverage of UAV missions. Bluetooth low energy (BLE) technology and the received signal strength indicator (RSSI) techniques have been proposed for target location during UAV landing. However, these RSSI-based techniques present a lack of precision due to the propagation medium characteristics, which leads to UAV position vagueness. In this sense, the development of a novel low-cost GLS system for UAV tracking and landing is proposed. The GLS system has been embodied for the purpose of testing the UAV landing navigation capability. The maximum likelihood estimator (MLE) algorithm is addressed on an embedded microcontroller for the position estimation based on the RSSI acquired from an array of BLE devices. Experimental results demonstrate the feasibility and accuracy of the ground landing station system, achieving average errors of less than 0.04 m with the UAV-MLE target position estimation approach. This 0.04 m distance represents an order of magnitude increase in location precision over other currently available solutions. In many cases, this increased precision can enable more innovative docking mechanisms, less likelihood of mishaps in docking, and also quicker docking. It may also facilitate docking procedures where the docking station is itself moving, which may be the case if the docking unit is a mobile ground rover

Energy Efficient Framework for a AIoT Cardiac Arrhythmia Detection System Wearable during Sport

The growing market of wearables is expanding into different areas of application such as devices designed to improve and monitor sport activities. This in turn is pushing research on low-cost, very low-power wearable systems with increased analysis capabilities. This paper proposes integrated energy-aware techniques and a convolutional neural network (CNN) for a cardiac arrhythmia detection system that can be worn during sport training sessions. The dynamic power management strategy (DPMS) is programmed into an ultra-low-power microcontroller, and in combination with a photovoltaic (PV) energy harvesting (EH) circuit, achieves a battery-life extension towards a self-powered operation. The CNN-based analysis filters, scales the image, and using a bicubic technique, interpolates the measurements to subsequently classify the electrocardiogram (ECG) signal into normal and abnormal patterns. Experimental results show that the EH-DPMS achieves an extension in the battery charge for a total of 14.34% more energy available, which represents 12 consecutive workouts of 45 min without the need to manually recharge it. Furthermore, an arrhythmia detection precision of 98.6% is achieved among the experimental sessions using 55,222 images for training the system with the MIT-BIH, QT, and long-term ST databases, and 1320 implemented on a wearable system. Therefore, the proposed wearable system can be used to monitor an athlete’s condition, reducing the risk of abnormal heart conditions during sports activities

Energy Efficient Framework for a AIoT Cardiac Arrhythmia Detection System Wearable during Sport

The growing market of wearables is expanding into different areas of application such as devices designed to improve and monitor sport activities. This in turn is pushing research on low-cost, very low-power wearable systems with increased analysis capabilities. This paper proposes integrated energy-aware techniques and a convolutional neural network (CNN) for a cardiac arrhythmia detection system that can be worn during sport training sessions. The dynamic power management strategy (DPMS) is programmed into an ultra-low-power microcontroller, and in combination with a photovoltaic (PV) energy harvesting (EH) circuit, achieves a battery-life extension towards a self-powered operation. The CNN-based analysis filters, scales the image, and using a bicubic technique, interpolates the measurements to subsequently classify the electrocardiogram (ECG) signal into normal and abnormal patterns. Experimental results show that the EH-DPMS achieves an extension in the battery charge for a total of 14.34% more energy available, which represents 12 consecutive workouts of 45 min without the need to manually recharge it. Furthermore, an arrhythmia detection precision of 98.6% is achieved among the experimental sessions using 55,222 images for training the system with the MIT-BIH, QT, and long-term ST databases, and 1320 implemented on a wearable system. Therefore, the proposed wearable system can be used to monitor an athlete’s condition, reducing the risk of abnormal heart conditions during sports activities

Libro Digital Proyectos Posgrados 2015-30

MaestríaDoctoradoDoctor en Ingeniería Eléctrica y ElectrónicaDoctor en Ingeniería CivilDoctor en Ingeniería de Sistemas y ComputaciónDoctor en Ingeniería IndustrialDoctor en Ingeniería MecánicaMagister en Gobierno de Tecnología InformáticaMagister en Ingeniería AdministrativaMagister en Ingeniería AmbientalMagister en Ingeniería CivilMagister en Ingeniería de Sistemas y ComputaciónMagister en Ingeniería EléctricaMagister en Ingeniería ElectrónicaMagister en Ingeniería IndustrialMagister en Ingeniería Mecánic