FEATURING SINGLE-AND MULTITHREADED EXECUTION, THE POWER5 PROVIDES HIGHER PERFORMANCE IN THE SINGLE-THREADED MODE THAN ITS POWER4 PREDECESSOR AT EQUIVALENT FREQUENCIES. ENHANCEMENTS IBM POWER5 CHIP: A DUAL-CORE MULTITHREADED PROCESSOR

IBM introduced Power4-based systems in 2001. 1 The Power4 design integrates two processor cores on a single chip, a shared second-level cache, a directory for an off-chip third-level cache, and the necessary circuitry to connect it to other Power4 chips to form a system. The dual-processor chip provides natural thread-level parallelism at the chip level. Additionally, the Power4's out-of-order execution design lets the hardware bypass instructions whose operands are not yet available (perhaps because of an earlier cache miss during register loading) and execute other instructions whose operands are ready. Later, when the operands become available, the hardware can execute the skipped instruction. Coupled with a superscalar design, out-of-order execution results in higher instruction execution parallelism than otherwise possible. The Power5 is the next-generation chip in this line. One of our key goals in designing the Power5 was to maintain both binary and structural compatibility with existing Power4 systems to ensure that binaries continue executing properly and all application optimizations carry forward to newer systems. With that base requirement, we specified increased performance and other functional enhancements of server virtualization, reliability, availability, and serviceability at both chip and system levels. In this article, we describe the approach we used to improve chip-level performance. Multithreading Conventional processors execute instructions from a single instruction stream. Despite microarchitectural advances, execution unit utilization remains low in today's microprocessors. It is not unusual to see average execution unit utilization rates of approximately 25 percent across a broad spectrum of environments. To increase execution unit utilization, designers use thread-level parallelism, in which the physical processor core executes instructions from more than one instruction stream. To the operating system, the physical processor core appears as if it is a symmetric multiprocessor containing two logical processors. There are at least three different methods for handling multiple threads. In coarse-grained multithreading, only on

STATE-CIVIL SOCIETY NETWORKS FOR POLICY IMPLEMENTATION IN DEVELOPING COUNTRIES -super-1

The emphasis in this article is on the trends which speak of governance rather than government. Governance refers to the role of citizens in the policy process and how groups within a society organize to make and implement decisions on matters of great concern. The focus is on democratic governance as taking place through networks in developing countries. These networks are referred to as state-civil society networks and are defined as cross-sectoral collaborations in which the view is not of individuals, per se, but rather of individual actors who are seen as a connected and interdependent whole. Three case studies of such state-civil society networks provide some preliminary lessons which suggest four situational variables for the emergence and success of these networks. These include: regime type, level of trust, legal framework and regulations, and the nature of the policy to be implemented. They also suggest some effective mechanisms and processes based on ad hoc vs formalizedmechanisms, initiation of the network and coordinating linkages. Copyright 1999 by The Policy Studies Organization.