Sincronización y Estimación de canal eficiente y robusta en sistemas CoMP OFDM

Este trabajo fue presentado en el XXIX Simposium Nacional de la Unión Científica Internacional de Radio, celebrado los días 3-5 de septiembre de 2014 en la Universidad Politécnica de Valencia (España).In this paper, an efficient and robust simultaneous timing synchronization and channel estimation method for Cooperative MultiPoint Transmission and Reception (CoMP) is proposed. Efficiency is obtained by using the same two Orthogonal Frequency Division Multiplexing (OFDM) symbols for simultaneously transmitting preambles by all the base stations. Robustness is achieved by specially designed orthogonal sequences both in time and frequency domain. The proposed method is able to estimate the channels from several base stations without losing anything in performance with respect to the single transmission scenario. Furthermore, our proposed synchronization outperforms single transmitter methods and so, it could also be adapted for single base station OFDM systems.Este trabajo ha sido financiado parcialmente por los proyectos GRE3NSYST (TEC2011-29006-C03-03) y COMONSENS (CSD2008-00010).Publicad

On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing

In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques. The convolution processing is based on the address–event-representation (AER) technique, which is a spike-based biologically inspired image and video representation technique that favors communication bandwidth for pixels with more information. As a first test prototype, a pixel array of 16x16 has been implemented with programmable kernel size of up to 16x16. The chip has been fabricated in a standard 0.35- m complimentary metal–oxide–semiconductor (CMOS) process. The technique also allows to process larger size images by assembling 2-D arrays of such chips. Pixel operation exploits low-power mixed analog–digital circuit techniques. Because of the low currents involved (down to nanoamperes or even picoamperes), an important amount of pixel area is devoted to mismatch calibration. The rest of the chip uses digital circuit techniques, both synchronous and asynchronous. The fabricated chip has been thoroughly tested, both at the pixel level and at the system level. Specific computer interfaces have been developed for generating AER streams from conventional computers and feeding them as inputs to the convolution chip, and for grabbing AER streams coming out of the convolution chip and storing and analyzing them on computers. Extensive experimental results are provided. At the end of this paper, we provide discussions and results on scaling up the approach for larger pixel arrays and multilayer cortical AER systems.Commission of the European Communities IST-2001-34124 (CAVIAR)Commission of the European Communities 216777 (NABAB)Ministerio de Educación y Ciencia TIC-2000-0406-P4Ministerio de Educación y Ciencia TIC-2003-08164-C03-01Ministerio de Educación y Ciencia TEC2006-11730-C03-01Junta de Andalucía TIC-141

An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links

Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation on silicon is, the higher the communication performance of the hosting platforms has to be. Many times the bottleneck of these system implementations is not on the performance inside a chip or a board, but in the communication between boards. This paper describes a novel modular Address-Event-Representation (AER) FPGA-based (Spartan6) infrastructure PCB (the AER-Node board) with 2.5Gbps LVDS high speed serial links over SATA cables that offers a peak performance of 32-bit 62.5Meps (Mega events per second) on board-to-board communications. The board allows back compatibility with parallel AER devices supporting up to x2 28-bit parallel data with asynchronous handshake. These boards also allow modular expansion functionality through several daughter boards. The paper is focused on describing in detail the LVDS serial interface and presenting its performance.Ministerio de Ciencia e Innovación TEC2009-10639-C04-02/01Ministerio de Economía y Competitividad TEC2012-37868-C04-02/01Junta de Andalucía TIC-6091Ministerio de Economía y Competitividad PRI-PIMCHI-2011-076

An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors

Event-Driven vision sensing is a new way of sensing visual reality in a frame-free manner. This is, the vision sensor (camera) is not capturing a sequence of still frames, as in conventional video and computer vision systems. In Event-Driven sensors each pixel autonomously and asynchronously decides when to send its address out. This way, the sensor output is a continuous stream of address events representing reality dynamically continuously and without constraining to frames. In this paper we present an Event-Driven Convolution Module for computing 2D convolutions on such event streams. The Convolution Module has been designed to assemble many of them for building modular and hierarchical Convolutional Neural Networks for robust shape and pose invariant object recognition. The Convolution Module has multi-kernel capability. This is, it will select the convolution kernel depending on the origin of the event. A proof-of-concept test prototype has been fabricated in a 0.35 m CMOS process and extensive experimental results are provided. The Convolution Processor has also been combined with an Event-Driven Dynamic Vision Sensor (DVS) for high-speed recognition examples. The chip can discriminate propellers rotating at 2 k revolutions per second, detect symbols on a 52 card deck when browsing all cards in 410 ms, or detect and follow the center of a phosphor oscilloscope trace rotating at 5 KHz.Unión Europea 216777 (NABAB)Ministerio de Ciencia e Innovación TEC2009-10639-C04-0

Learning Mobile Communications Standards through Flexible Software Defined Radio Base Stations

Mobile communications are today widespread and contribute to the development of our society. Every day new devices include some means of wireless transmission, which is becoming ubiquitous with the Internet of Things. These systems are standardized by international organizations such as the IEEE, 3GPP, and ETSI, among others. Even though knowledge of wireless standards is key to the understanding of these systems, wireless communications are quite often taught in engineering degrees in a traditional way, without much emphasis on the standardization. Moreover, strong focus is often placed on the theoretical performance analysis rather than on practical implementation aspects. In contrast, most of the current applications make extensive use of mobile data, and the global users' satisfaction is highly correlated with the mobile data throughput. Thus, modern wireless engineers need to have deep insight on the standards that define the mobile transmission systems, and this knowledge is not acquired following the traditional theoretical teaching schemes. In this article, a new learning approach is described. This novel paradigm is based on a new flexible hardware/software platform (FRAMED-SOFT), which is also detailed. Although the article is focused on two wireless standards, GSM and UMTS, the work discussed in this article can easily be extended to other standards of interest, such as LTE and beyond, WiFi, and WiMAX

Spike-based VITE control with Dynamic Vision Sensor applied to an Arm Robot.

Spike-based motor control is very important in the field of robotics and also for the neuromorphic engineering community to bridge the gap between sensing / processing devices and motor control without losing the spike philosophy that enhances speed response and reduces power consumption. This paper shows an accurate neuro-inspired spike-based system composed of a DVS retina, a visual processing system that detects and tracks objects, and a SVITE motor control, where everything follows the spike-based philosophy. The control system is a spike version of the neuroinspired open loop VITE control algorithm implemented in a couple of FPGA boards: the first one runs the algorithm and the second one drives the motors with spikes. The robotic platform is a low cost arm with four degrees of freedom.Ministerio de Ciencia e Innovación TEC2009-10639-C04-02/01Ministerio de Economía y Competitividad TEC2012-37868-C04-02/0

De tumba a iglesia. Análisis arqueológico y arquitectónico del complejo funerario del Reino Antiguo (QH34h) y su transformación en iglesia cristiana bizantina en la necrópolis de Qubbet el Hawa (Asuán, Egipto)

The archaeological site of Qubbet el Hawa contains one of the largest necropolis in southern Egypt. At this burial site the governors and high officials of the southernmost province of Egypt were buried from the Late Old Kingdom to the Late 12th Dynasty. This study aims to analyze one of the largest funerary complexes (QH34h), belonging to the local governor Khunes, and other annexed tombs of his relatives. This large funerary complex, with a great funerary chapel, includes an ascending stairway and a monumental courtyard. It was built during the last part of the reign of Pepy II (2216-2153 BC). It underwent a set of architectural transformations throughout its history, including several collapses and, centuries later, it was chosen by a Coptic community to establish a Christian church and other monastic places. The main aim of the present paper is to analyze how the sacred space changed over time and the architectonic spaces were used with different purposes.El yacimiento arqueológico de Qubbet el-Hawa alberga una de las mayores necrópolis del sur de Egipto. En ella se enterraron los altos dignatarios y los nobles que gobernaron la provincia más meridional de Egipto desde el Reino Antiguo (al menos la VI dinastía) hasta el Reino Medio (Dinastía XII). Se han llegado a documentar más de 70 hipogeos, alguno de los cuales aún siguen sin ser investigados en profundidad. El trabajo que aquí presentamos trata de comprender uno de los complejos funerarios más grandes y antiguos de la necrópolis, compuesto por la tumba conocida como QH34h, que perteneció al gobernador Khunes y las tumbas anexas de sus familiares. Fue construido hacia el final del reinado de Pepy II (2216-2153 a. C.), sufrió una serie de transformaciones arquitectónicas a lo largo de su historia, derrumbes importantes y finalmente fue elegido por una comunidad monástica para establecer en él una iglesia cristiana en el siglo VI. El objetivo principal de este artículo es analizar cómo un espacio sagrado cambió a lo largo del tiempo y los diferentes espacios arquitectónicos fueron usados en diferentes propósitos