A High-Speed Range-Matching TCAM for Storage-Efficient Packet Classification

Abstract—A critical issue in the use of TCAMs for packet classification is how to efficiently represent rules with ranges, known as range matching. A range-matching ternary content addressable memory (RM-TCAM) including a highly functional range-matching cell (RMC) is presented in this paper. By offering various range operators, the RM-TCAM can reduce storage expansion ratio from 4.21 to 1.01 compared with conventional TCAMs, under real-world packet classification rule sets, which results in reduced power consumption and die area. A new pre-discharging match-line scheme is used to realize high-speed searching in a dynamic match-line structure. An additional charge-recycling driver further reduces the power consumption of search lines. Simulation results of a 256 64-bit range-matching TCAM, when implemented in the 0.13- m CMOS technology, achieves a 1.99-ns search time with an energy efficiency of 1.26 fJ/bit/search. While a TCAM including range encoding approach requires an additional SRAM or DRAM, the RM-TCAM can improve storage efficiency without any extra components as well as reduce the die area

A 1.35GHz All-Digital Fractional-N PLL with Adaptive Loop Gain Controller and Fractional Divider

A 1.35GHz all-digital phase-locked loop (ADPLL) with an adaptively controlled loop filter and a 1/3rd-resolution fractional divider is presented. The adaptive loop gain controller (ALGC) effectively reduces the nonlinear characteristics of the bang-bang phase-frequency detector (BBPFD). The fractional divider partially compensates for the input phase error which is caused by the fractional-N frequency synthesis operation. A prototype ADPLL using a BBPFD with a dead zone free retimer, an ALGC, and a fractional divider is fabricated in 0.13m CMOS. The core occupies 0.19mm2 and consumes 13.7mW from a 1.2V supply. The measured RMS jitter was 4.17ps at a 1.35GHz clock output

A Crystal-Less Programmable Clock Generator With RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS

This paper presents a crystal-less programmable clock generator. The programmable clock generator takes advantages of both RC and LC oscillators. The frequency reference is generated by the RC oscillator without using expensive external crystals. The sawtooth signal generated from the RC oscillator is sampled by low phase-noise differential clocks which are divided from the LC oscillator. The timing information is then amplified by the sampler which uses hysteresis. An additional block, gain adjuster (GA), reduces lock time and dithering. After the system gets locked, it achieves 0.01 %/V and 25.5 ppm/degrees C frequency variations for 100 MHz generated clock. The 14 nm FinFET CMOS programmable clock generator draws 28 mA current from a single 1.8 V supply and occupies an active area of 0.12 mm(2)(.) It achieves 163 dBc/Hz FoM for 100 MHz test clock.N

Design of High Step-Down Ratio Isolated Three-Level Half-Bridge DC-DC Converter With Balanced Voltage on Flying Capacitor

A high step-down ratio three-level half-bridge (TLHB) dc-dc converter with a current-doubler rectifier is presented for power conversion from a 48-to-60-V input to a 0.5-to-1-V output. The proposed TLHB topology and operation employed on the primary side improve the power-conversion efficiency by reducing the switching loss while minimizing the turn ratio of the transformer by converting the input voltage down to one quarter on the primary side. Moreover, it reduces the voltage stress on switches by half, thereby enabling the converter to be implemented with Si transistors with low breakdown voltage. The designed TLHB gate-driver IC minimizes the delay mismatches in gate drivers and mitigates the effect of the leakage inductance of the transformer, reducing the voltage imbalance on the flying capacitor without any balancing scheme in the controller. The proposed dc-dc converter implemented with 40-V Si transistors for the primary-side switches achieves 92.8% peak efficiency while supporting the maximum load current of 60 A and the maximum input voltage of 60 V. The converter with the proposed TLHB gate driver IC shows less than 0.8% voltage imbalance on the flying capacitor.N

Design of Soft-Switching Hybrid DC-DC Converter with 2-Phase Switched Capacitor and 0.8nH Inductor for Standard CMOS Process

A soft-switching hybrid DC-DC converter with a 2-phase switched capacitor is proposed for the implementation of a fully-integrated voltage regulator in a 65 nm standard CMOS process. The soft-switching operation is implemented to minimize power loss due to the parasitic capacitance of the flying capacitor. The 2-phase switched capacitor topology keeps the same resonance value for every soft-switching operation, resulting in minimizing the voltage imbalance of the flying capacitor. The proposed adaptive timing generator digitally calibrates the turn-on delay of switches to achieve a complete soft-switching operation. The simulation results show that the proposed soft-switching hybrid DC-DC converter with a 2-phase 2:1 switched capacitor improves the efficiency by 5.1% and achieves 79.5% peak efficiency at a maximum load current of 250 mA

Analysis and design of cmos clocking circuits for low phase noise

As electronics continue to become faster, smaller and more efficient, development and research around clocking signals and circuits has accelerated to keep pace. This book bridges the gap between the classical theory of clocking circuits and recent technological advances

A Fully Integrated 700mA Event-Driven Digital Low-Dropout Regulator with Residue-Tracking Loop for Fine-Grained Power Management Unit

This paper presents a fully integrated digital low-dropout regulator (LDO). A proposed event-driven digital control based on a residue-tracking loop provides not only a heavy load capacity of 700mA but also an accurate regulation. A latch-based shift register is adopted to improve the digital regulation against a large load current change. The proposed LDO embedding an on-chip 100pF output capacitor was fabricated in a 65nm LP CMOS process. The LDO provides a load regulation of 0.1mV/mA and an output voltage error below 1.1% across a range from 0.5 to 1V. The LDO achieves a figure-of-merit (FOM) of 6.74fs.N

A Maximum-Eye-Tracking CDR with Biased Data-Level and Eye Slope Detector for Optimal Timing Adaptation

In this paper, a maximum-eye-tracking CDR (MET-CDR) for minimum bit error rate (BER) is presented. The proposed CDR does not require a BER counter or eye-opening monitor to find the optimal sampling phase. The biased datalevel obtained from the weighted sum of UP and DN is proposed to extract the actual eye height information considering the precursor ISI. Two error samples with small time spacing detect the current eye height and the slope of the eye height so that the CDR tracks the maximum eye height where the slope becomes zero. Measured results prove that the maximum eye height phase and the minimum BER phase matches well. A prototype receiver fabricated in 28-nm CMOS process operates at 26Gb/s with an eye-opening of 25% UI and consumes 87mW while equalizing 21dB of loss at 13GHz.N